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aa8ba5166e
Replace pending 730-net-phy-at803x-fix-feature-detection.patch with upstream version and move it to backport. Refresh other related patch while moving it. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
230 lines
6.2 KiB
Diff
230 lines
6.2 KiB
Diff
From 272833b9b3b3969be7a91839121d86662c8c4253 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 14 May 2021 23:00:15 +0200
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Subject: [PATCH] net: phy: add support for qca8k switch internal PHY in at803x
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Since the at803x share the same regs, it's assumed they are based on the
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same implementation. Make it part of the at803x PHY driver to skip
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having redudant code.
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Add initial support for qca8k internal PHYs. The internal PHYs requires
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special mmd and debug values to be set based on the switch revision
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passwd using the dev_flags. Supports output of idle, receive and eee_wake
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errors stats.
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Some debug values sets can't be translated as the documentation lacks any
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reference about them.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/Kconfig | 5 +-
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drivers/net/phy/at803x.c | 132 ++++++++++++++++++++++++++++++++++++++-
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2 files changed, 134 insertions(+), 3 deletions(-)
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -235,10 +235,11 @@ config NXP_TJA11XX_PHY
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Currently supports the NXP TJA1100 and TJA1101 PHY.
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config AT803X_PHY
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- tristate "Qualcomm Atheros AR803X PHYs"
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+ tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
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depends on REGULATOR
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help
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- Currently supports the AR8030, AR8031, AR8033 and AR8035 model
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+ Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
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+ QCA8337(Internal qca8k PHY) model
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config QSEMI_PHY
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tristate "Quality Semiconductor PHYs"
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--- a/drivers/net/phy/at803x.c
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+++ b/drivers/net/phy/at803x.c
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@@ -92,10 +92,16 @@
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#define AT803X_DEBUG_REG_5 0x05
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#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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+#define AT803X_DEBUG_REG_3C 0x3C
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+
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+#define AT803X_DEBUG_REG_3D 0x3D
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+
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#define AT803X_DEBUG_REG_1F 0x1F
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#define AT803X_DEBUG_PLL_ON BIT(2)
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#define AT803X_DEBUG_RGMII_1V8 BIT(3)
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+#define MDIO_AZ_DEBUG 0x800D
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+
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/* AT803x supports either the XTAL input pad, an internal PLL or the
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* DSP as clock reference for the clock output pad. The XTAL reference
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* is only used for 25 MHz output, all other frequencies need the PLL.
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@@ -142,10 +148,34 @@
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#define AT803X_PAGE_FIBER 0
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#define AT803X_PAGE_COPPER 1
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+#define QCA8327_PHY_ID 0x004dd034
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+#define QCA8337_PHY_ID 0x004dd036
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+#define QCA8K_PHY_ID_MASK 0xffffffff
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+
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+#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
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+
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MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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+enum stat_access_type {
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+ PHY,
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+ MMD
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+};
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+
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+struct at803x_hw_stat {
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+ const char *string;
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+ u8 reg;
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+ u32 mask;
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+ enum stat_access_type access_type;
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+};
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+
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+static struct at803x_hw_stat at803x_hw_stats[] = {
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+ { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
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+ { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
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+ { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
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+};
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+
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struct at803x_priv {
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int flags;
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#define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
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@@ -154,6 +184,7 @@ struct at803x_priv {
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struct regulator_dev *vddio_rdev;
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struct regulator_dev *vddh_rdev;
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struct regulator *vddio;
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+ u64 stats[ARRAY_SIZE(at803x_hw_stats)];
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};
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struct at803x_context {
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@@ -165,6 +196,17 @@ struct at803x_context {
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u16 led_control;
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};
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+static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
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+{
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+ int ret;
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+
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+ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ return phy_write(phydev, AT803X_DEBUG_DATA, data);
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+}
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+
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static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
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{
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int ret;
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@@ -327,6 +369,53 @@ static void at803x_get_wol(struct phy_de
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wol->wolopts |= WAKE_MAGIC;
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}
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+static int at803x_get_sset_count(struct phy_device *phydev)
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+{
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+ return ARRAY_SIZE(at803x_hw_stats);
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+}
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+
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+static void at803x_get_strings(struct phy_device *phydev, u8 *data)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
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+ strscpy(data + i * ETH_GSTRING_LEN,
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+ at803x_hw_stats[i].string, ETH_GSTRING_LEN);
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+ }
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+}
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+
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+static u64 at803x_get_stat(struct phy_device *phydev, int i)
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+{
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+ struct at803x_hw_stat stat = at803x_hw_stats[i];
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+ struct at803x_priv *priv = phydev->priv;
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+ int val;
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+ u64 ret;
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+
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+ if (stat.access_type == MMD)
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+ val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
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+ else
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+ val = phy_read(phydev, stat.reg);
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+
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+ if (val < 0) {
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+ ret = U64_MAX;
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+ } else {
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+ val = val & stat.mask;
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+ priv->stats[i] += val;
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+ ret = priv->stats[i];
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+ }
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+
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+ return ret;
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+}
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+
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+static void at803x_get_stats(struct phy_device *phydev,
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+ struct ethtool_stats *stats, u64 *data)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
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+ data[i] = at803x_get_stat(phydev, i);
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+}
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+
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static int at803x_suspend(struct phy_device *phydev)
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{
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int value;
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@@ -1130,6 +1219,34 @@ static int at803x_cable_test_start(struc
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return 0;
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}
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+static int qca83xx_config_init(struct phy_device *phydev)
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+{
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+ u8 switch_revision;
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+
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+ switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
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+
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+ switch (switch_revision) {
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+ case 1:
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+ /* For 100M waveform */
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);
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+ /* Turn on Gigabit clock */
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);
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+ break;
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+
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+ case 2:
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+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
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+ fallthrough;
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+ case 4:
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static struct phy_driver at803x_driver[] = {
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{
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/* Qualcomm Atheros AR8035 */
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@@ -1226,7 +1343,20 @@ static struct phy_driver at803x_driver[]
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.read_status = at803x_read_status,
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.soft_reset = genphy_soft_reset,
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.config_aneg = at803x_config_aneg,
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-} };
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+}, {
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+ /* QCA8337 */
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+ .phy_id = QCA8337_PHY_ID,
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+ .phy_id_mask = QCA8K_PHY_ID_MASK,
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+ .name = "QCA PHY 8337",
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+ /* PHY_GBIT_FEATURES */
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+ .probe = at803x_probe,
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+ .flags = PHY_IS_INTERNAL,
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+ .config_init = qca83xx_config_init,
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+ .soft_reset = genphy_soft_reset,
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+ .get_sset_count = at803x_get_sset_count,
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+ .get_strings = at803x_get_strings,
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+ .get_stats = at803x_get_stats,
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+}, };
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module_phy_driver(at803x_driver);
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