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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
307 lines
8.2 KiB
Diff
307 lines
8.2 KiB
Diff
From 243b040c3517093309a41877e3c1c6e8a7540071 Mon Sep 17 00:00:00 2001
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From: Jack Zhu <jack.zhu@starfivetech.com>
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Date: Tue, 23 May 2023 16:56:22 +0800
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Subject: [PATCH 076/122] media: dt-bindings: cadence-csi2rx: Convert to DT
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schema
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Convert DT bindings document for Cadence MIPI-CSI2 RX controller to
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DT schema format.
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For compatible, new compatibles should not be messed with conversion,
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but the original binding did not specify any SoC-specific compatible
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string, so add the StarFive compatible string.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
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---
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.../devicetree/bindings/media/cdns,csi2rx.txt | 100 ----------
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.../bindings/media/cdns,csi2rx.yaml | 177 ++++++++++++++++++
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2 files changed, 177 insertions(+), 100 deletions(-)
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delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt
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create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
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--- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt
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+++ /dev/null
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@@ -1,100 +0,0 @@
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-Cadence MIPI-CSI2 RX controller
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-===============================
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-
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-The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
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-lanes in input, and 4 different pixel streams in output.
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-
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-Required properties:
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- - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
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- - reg: base address and size of the memory mapped region
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- - clocks: phandles to the clocks driving the controller
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- - clock-names: must contain:
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- * sys_clk: main clock
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- * p_clk: register bank clock
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- * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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- implemented in hardware, between 0 and 3
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-
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-Optional properties:
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- - phys: phandle to the external D-PHY, phy-names must be provided
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- - phy-names: must contain "dphy", if the implementation uses an
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- external D-PHY
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-
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-Required subnodes:
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- - ports: A ports node with one port child node per device input and output
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- port, in accordance with the video interface bindings defined in
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- Documentation/devicetree/bindings/media/video-interfaces.txt. The
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- port nodes are numbered as follows:
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-
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- Port Description
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- -----------------------------
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- 0 CSI-2 input
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- 1 Stream 0 output
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- 2 Stream 1 output
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- 3 Stream 2 output
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- 4 Stream 3 output
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-
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- The stream output port nodes are optional if they are not
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- connected to anything at the hardware level or implemented
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- in the design.Since there is only one endpoint per port,
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- the endpoints are not numbered.
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-
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-
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-Example:
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-
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-csi2rx: csi-bridge@0d060000 {
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- compatible = "cdns,csi2rx";
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- reg = <0x0d060000 0x1000>;
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- clocks = <&byteclock>, <&byteclock>
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- <&coreclock>, <&coreclock>,
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- <&coreclock>, <&coreclock>;
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- clock-names = "sys_clk", "p_clk",
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- "pixel_if0_clk", "pixel_if1_clk",
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- "pixel_if2_clk", "pixel_if3_clk";
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-
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- ports {
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- port@0 {
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- reg = <0>;
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-
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- csi2rx_in_sensor: endpoint {
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- remote-endpoint = <&sensor_out_csi2rx>;
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- clock-lanes = <0>;
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- data-lanes = <1 2>;
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- };
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- };
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-
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- port@1 {
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- reg = <1>;
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-
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- csi2rx_out_grabber0: endpoint {
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- remote-endpoint = <&grabber0_in_csi2rx>;
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- };
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- };
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-
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- port@2 {
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- reg = <2>;
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-
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- csi2rx_out_grabber1: endpoint {
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- remote-endpoint = <&grabber1_in_csi2rx>;
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- };
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- };
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-
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- port@3 {
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- reg = <3>;
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-
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- csi2rx_out_grabber2: endpoint {
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- remote-endpoint = <&grabber2_in_csi2rx>;
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- };
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- };
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-
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- port@4 {
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- reg = <4>;
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-
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- csi2rx_out_grabber3: endpoint {
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- remote-endpoint = <&grabber3_in_csi2rx>;
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- };
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- };
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- };
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-};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
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@@ -0,0 +1,177 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Cadence MIPI-CSI2 RX controller
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+
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+maintainers:
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+ - Maxime Ripard <mripard@kernel.org>
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+
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+description:
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+ The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
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+ lanes in input, and 4 different pixel streams in output.
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+
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+properties:
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+ compatible:
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+ items:
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+ - enum:
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+ - starfive,jh7110-csi2rx
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+ - const: cdns,csi2rx
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: CSI2Rx system clock
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+ - description: Gated Register bank clock for APB interface
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+ - description: pixel Clock for Stream interface 0
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+ - description: pixel Clock for Stream interface 1
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+ - description: pixel Clock for Stream interface 2
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+ - description: pixel Clock for Stream interface 3
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+
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+ clock-names:
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+ items:
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+ - const: sys_clk
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+ - const: p_clk
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+ - const: pixel_if0_clk
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+ - const: pixel_if1_clk
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+ - const: pixel_if2_clk
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+ - const: pixel_if3_clk
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+
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+ phys:
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+ maxItems: 1
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+ description: MIPI D-PHY
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+
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+ phy-names:
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+ items:
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+ - const: dphy
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+
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+ ports:
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+ $ref: /schemas/graph.yaml#/properties/ports
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+
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+ properties:
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+ port@0:
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+ $ref: /schemas/graph.yaml#/$defs/port-base
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+ unevaluatedProperties: false
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+ description:
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+ Input port node, single endpoint describing the CSI-2 transmitter.
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+
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+ properties:
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+ endpoint:
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+ $ref: video-interfaces.yaml#
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+ unevaluatedProperties: false
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+
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+ properties:
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+ bus-type:
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+ const: 4
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+
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+ clock-lanes:
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+ const: 0
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+
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+ data-lanes:
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+ minItems: 1
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+ maxItems: 4
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+ items:
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+ maximum: 4
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+
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+ required:
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+ - data-lanes
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+
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+ port@1:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description:
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+ Stream 0 Output port node
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+
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+ port@2:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description:
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+ Stream 1 Output port node
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+
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+ port@3:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description:
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+ Stream 2 Output port node
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+
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+ port@4:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description:
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+ Stream 3 Output port node
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+
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+ required:
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+ - port@0
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - ports
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ csi@d060000 {
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+ compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
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+ reg = <0x0d060000 0x1000>;
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+ clocks = <&byteclock 7>, <&byteclock 6>,
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+ <&coreclock 8>, <&coreclock 9>,
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+ <&coreclock 10>, <&coreclock 11>;
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+ clock-names = "sys_clk", "p_clk",
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+ "pixel_if0_clk", "pixel_if1_clk",
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+ "pixel_if2_clk", "pixel_if3_clk";
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+ phys = <&csi_phy>;
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+ phy-names = "dphy";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+
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+ csi2rx_in_sensor: endpoint {
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+ remote-endpoint = <&sensor_out_csi2rx>;
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+ clock-lanes = <0>;
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+ data-lanes = <1 2>;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+
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+ csi2rx_out_grabber0: endpoint {
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+ remote-endpoint = <&grabber0_in_csi2rx>;
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+ };
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+
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+ csi2rx_out_grabber1: endpoint {
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+ remote-endpoint = <&grabber1_in_csi2rx>;
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+ };
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+
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+ csi2rx_out_grabber2: endpoint {
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+ remote-endpoint = <&grabber2_in_csi2rx>;
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+ };
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+
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+ csi2rx_out_grabber3: endpoint {
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+ remote-endpoint = <&grabber3_in_csi2rx>;
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+ };
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+ };
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+ };
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+ };
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+
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+...
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