mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
72 lines
1.8 KiB
Diff
72 lines
1.8 KiB
Diff
From 99f0bf43994dada29e33fd8718fd25484634da3a Mon Sep 17 00:00:00 2001
|
|
From: William Qiu <william.qiu@starfivetech.com>
|
|
Date: Tue, 21 Mar 2023 13:52:27 +0800
|
|
Subject: [PATCH 062/122] dt-bindings: PWM: Add StarFive PWM module
|
|
|
|
Add documentation to describe StarFive Pulse Width Modulation
|
|
controller driver.
|
|
|
|
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
|
|
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
---
|
|
.../bindings/pwm/starfive,jh7110-pwm.yaml | 53 +++++++++++++++++++
|
|
1 file changed, 53 insertions(+)
|
|
create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
|
|
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
|
|
@@ -0,0 +1,53 @@
|
|
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
|
+%YAML 1.2
|
|
+---
|
|
+$id: http://devicetree.org/schemas/pwm/starfive,jh7110-pwm.yaml#
|
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
+
|
|
+title: StarFive PWM controller
|
|
+
|
|
+maintainers:
|
|
+ - William Qiu <william.qiu@starfivetech.com>
|
|
+
|
|
+description:
|
|
+ StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates
|
|
+ binary signal with user-programmable low and high periods. Clock source for the
|
|
+ PWM can be either system clockor external clock. Each PWM timer block provides 8
|
|
+ PWM channels.
|
|
+
|
|
+allOf:
|
|
+ - $ref: pwm.yaml#
|
|
+
|
|
+properties:
|
|
+ compatible:
|
|
+ const: starfive,jh7110-pwm
|
|
+
|
|
+ reg:
|
|
+ maxItems: 1
|
|
+
|
|
+ clocks:
|
|
+ maxItems: 1
|
|
+
|
|
+ resets:
|
|
+ maxItems: 1
|
|
+
|
|
+ "#pwm-cells":
|
|
+ const: 3
|
|
+
|
|
+required:
|
|
+ - compatible
|
|
+ - reg
|
|
+ - clocks
|
|
+ - resets
|
|
+
|
|
+additionalProperties: false
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ pwm@120d0000 {
|
|
+ compatible = "starfive,jh7110-pwm";
|
|
+ reg = <0x120d0000 0x10000>;
|
|
+ clocks = <&syscrg 121>;
|
|
+ resets = <&syscrg 108>;
|
|
+ #pwm-cells = <3>;
|
|
+ };
|