openwrt/target/linux/octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
Hauke Mehrtens 26d1d52403 kernel: bump 5.15 to 5.15.149
Removed because it is upstream:
generic/pending-5.15/540-ksmbd-only-v2-leases-handle-the-directory.patch
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=81ea755b8fa57ce186f56f14b709cf491c2a5505

Manually Adapted the following patch:
ath79/patches-5.15/900-unaligned_access_hacks.patch

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2024-03-07 19:30:54 +01:00

60 lines
1.9 KiB
Diff

From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 10 Apr 2019 08:00:47 -0700
Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with
GPIO PERST#
Gateworks boards use PLX PEX860x switches where downstream ports
have their PERST# driven from the PEX GPIO.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
#include <linux/ktime.h>
#include <linux/mm.h>
#include <linux/nvme.h>
+#include <linux/of.h>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
@@ -5899,3 +5900,34 @@ static void nvidia_ion_ahci_fixup(struct
pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
+
+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
+/*
+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
+ * as they are used for slots1-7 PERST#
+ */
+static void newport_pciesw_early_fixup(struct pci_dev *dev)
+{
+ u32 dw;
+
+ if (!of_machine_is_compatible("gw,newport"))
+ return;
+
+ if (dev->devfn != 0)
+ return;
+
+ dev_info(&dev->dev, "de-asserting PERST#\n");
+ pci_read_config_dword(dev, 0x62c, &dw);
+ dw |= 0xaaa8; /* GPIO1-7 outputs */
+ pci_write_config_dword(dev, 0x62c, dw);
+
+ pci_read_config_dword(dev, 0x644, &dw);
+ dw |= 0xfe; /* GPIO1-7 output high */
+ pci_write_config_dword(dev, 0x644, dw);
+
+ msleep(100);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);
+#endif /* CONFIG_PCI_HOST_THUNDER_PEM */