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This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
39 lines
1.1 KiB
Diff
39 lines
1.1 KiB
Diff
From 20a204b31291befcd583f97dafc0a827f3bc7f00 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Fri, 12 Aug 2022 01:37:16 -0500
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Subject: [PATCH 099/117] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts
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property
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The sun6i DPHY can generate several interrupts, mostly for reporting
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error conditions, but also for detecting BTA and UPLS sequences.
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Document this capability in order to accurately describe the hardware.
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The DPHY has no interrupt number provided in the vendor documentation
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because its interrupt line is shared with the DSI controller.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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.../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
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+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
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@@ -24,6 +24,9 @@ properties:
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reg:
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maxItems: 1
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+ interrupts:
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+ maxItems: 1
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+
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clocks:
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items:
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- description: Bus Clock
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@@ -53,6 +56,7 @@ required:
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- "#phy-cells"
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- compatible
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- reg
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+ - interrupts
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- clocks
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- clock-names
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- resets
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