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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
111 lines
4.1 KiB
Diff
111 lines
4.1 KiB
Diff
From 9a7acb8f03346705d7420a490d95b32309d90e22 Mon Sep 17 00:00:00 2001
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From: Roman Beranek <roman.beranek@prusa3d.com>
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Date: Wed, 25 Nov 2020 13:07:35 +0100
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Subject: [PATCH 086/117] drm/sun4i: decouple TCON_DCLK_DIV value from
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pll_mipi/dotclock ratio
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Observations showed that an actual refresh rate differs from the intended.
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Specifically, in case of 4-lane panels it was reduced by 1/3, and in case of
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2-lane panels by 2/3.
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BSP code apparently distinguishes between a `dsi_div` and a 'tcon inner div'.
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While this 'inner' divider is under DSI always 4, the `dsi_div` is defined
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as a number of bits per pixel over a number of DSI lanes. This value is then
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involved in setting the rate of PLL_MIPI.
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I couldn't really figure out how to fit this into the dotclock driver,
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so I opted for this hack where the requested rate is adjusted in such a way
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that the sun4i_dotclock driver can remain untouched.
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Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/gpu/drm/sun4i/sun4i_tcon.c | 44 +++++++++++++++++-------------
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1 file changed, 25 insertions(+), 19 deletions(-)
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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@@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(cons
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return delay;
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}
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-static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
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- const struct drm_display_mode *mode)
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-{
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- /* Configure the dot clock */
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- clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
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-
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- /* Set the resolution */
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- regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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- SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
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- SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
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-}
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-
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static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
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const struct drm_connector *connector)
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{
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@@ -365,12 +353,18 @@ static void sun4i_tcon0_mode_set_cpu(str
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u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
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u8 lanes = device->lanes;
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u32 block_space, start_delay;
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- u32 tcon_div;
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tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
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tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
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- sun4i_tcon0_mode_set_common(tcon, mode);
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+ /* Configure the dot clock */
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+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000
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+ * bpp / (lanes * SUN6I_DSI_TCON_DIV));
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+
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+ /* Set the resolution */
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+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
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+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
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/* Set dithering if needed */
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sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
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@@ -394,9 +388,7 @@ static void sun4i_tcon0_mode_set_cpu(str
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* The datasheet says that this should be set higher than 20 *
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* pixel cycle, but it's not clear what a pixel cycle is.
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*/
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- regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
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- tcon_div &= GENMASK(6, 0);
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- block_space = mode->htotal * bpp / (tcon_div * lanes);
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+ block_space = mode->htotal * bpp / (SUN6I_DSI_TCON_DIV * lanes);
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block_space -= mode->hdisplay + 40;
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regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
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@@ -438,7 +430,14 @@ static void sun4i_tcon0_mode_set_lvds(st
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tcon->dclk_min_div = 7;
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tcon->dclk_max_div = 7;
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- sun4i_tcon0_mode_set_common(tcon, mode);
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+
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+ /* Configure the dot clock */
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+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
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+
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+ /* Set the resolution */
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+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
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+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
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/* Set dithering if needed */
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sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
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@@ -515,7 +514,14 @@ static void sun4i_tcon0_mode_set_rgb(str
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tcon->dclk_min_div = tcon->quirks->dclk_min_div;
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tcon->dclk_max_div = 127;
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- sun4i_tcon0_mode_set_common(tcon, mode);
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+
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+ /* Configure the dot clock */
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+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
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+
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+ /* Set the resolution */
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+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
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+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
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/* Set dithering if needed */
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sun4i_tcon0_mode_set_dithering(tcon, connector);
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