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c09eb08dad
Import pending patches to support the upcoming Filogic platforms. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
553 lines
14 KiB
Diff
553 lines
14 KiB
Diff
From a299de45833df13d4ec28092201ea5fec0ba24fe Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 29 Jul 2022 15:17:58 +0800
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Subject: [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC
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This patch adds basic support for MediaTek MT7986 SoC.
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This include the file that will initialize the SoC after boot and its
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device tree.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/arm/dts/mt7986-u-boot.dtsi | 33 ++
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arch/arm/dts/mt7986.dtsi | 341 ++++++++++++++++++
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arch/arm/mach-mediatek/Kconfig | 11 +
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arch/arm/mach-mediatek/Makefile | 1 +
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arch/arm/mach-mediatek/mt7986/Makefile | 4 +
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arch/arm/mach-mediatek/mt7986/init.c | 51 +++
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arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 32 ++
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7 files changed, 473 insertions(+)
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create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi
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create mode 100644 arch/arm/dts/mt7986.dtsi
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create mode 100644 arch/arm/mach-mediatek/mt7986/Makefile
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create mode 100644 arch/arm/mach-mediatek/mt7986/init.c
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create mode 100644 arch/arm/mach-mediatek/mt7986/lowlevel_init.S
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--- /dev/null
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+++ b/arch/arm/dts/mt7986-u-boot.dtsi
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@@ -0,0 +1,33 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+&topckgen {
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+ u-boot,dm-pre-reloc;
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+};
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+
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+&pericfg {
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+ u-boot,dm-pre-reloc;
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+};
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+
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+&apmixedsys {
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+ u-boot,dm-pre-reloc;
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+};
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+
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+&timer0 {
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+ u-boot,dm-pre-reloc;
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+};
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+
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+&uart0 {
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+ u-boot,dm-pre-reloc;
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+};
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+
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+&snand {
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+ u-boot,dm-pre-reloc;
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+};
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+
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+&pinctrl {
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+ u-boot,dm-pre-reloc;
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+};
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--- /dev/null
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+++ b/arch/arm/dts/mt7986.dtsi
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@@ -0,0 +1,341 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/phy/phy.h>
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+#include <dt-bindings/clock/mt7986-clk.h>
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+#include <dt-bindings/reset/mt7629-reset.h>
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+#include <dt-bindings/pinctrl/mt65xx.h>
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+
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+/ {
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+ compatible = "mediatek,mt7986";
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+ interrupt-parent = <&gic>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ config {
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+ u-boot,mmc-env-partition = "u-boot-env";
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0>;
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+ };
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x1>;
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+ };
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x1>;
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+ };
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x1>;
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+ };
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+ };
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+
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+ dummy_clk: dummy12m {
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+ compatible = "fixed-clock";
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+ clock-frequency = <12000000>;
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+ #clock-cells = <0>;
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+ /* must need this line, or uart uanable to get dummy_clk */
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+ u-boot,dm-pre-reloc;
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupt-parent = <&gic>;
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+ clock-frequency = <13000000>;
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+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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+ arm,cpu-registers-not-fw-configured;
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+ };
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+
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+ timer0: timer@10008000 {
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+ compatible = "mediatek,mt7986-timer";
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+ reg = <0x10008000 0x1000>;
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+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CK_INFRA_CK_F26M>;
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+ clock-names = "gpt-clk";
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+ u-boot,dm-pre-reloc;
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+ };
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+
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+ watchdog: watchdog@1001c000 {
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+ compatible = "mediatek,mt7986-wdt";
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+ reg = <0x1001c000 0x1000>;
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+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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+ #reset-cells = <1>;
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+ status = "disabled";
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+ };
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+
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+ gic: interrupt-controller@c000000 {
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+ compatible = "arm,gic-v3";
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+ #interrupt-cells = <3>;
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+ interrupt-parent = <&gic>;
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+ interrupt-controller;
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+ reg = <0x0c000000 0x40000>, /* GICD */
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+ <0x0c080000 0x200000>; /* GICR */
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+
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+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ fixed_plls: apmixedsys@1001E000 {
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+ compatible = "mediatek,mt7986-fixed-plls";
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+ reg = <0x1001E000 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ topckgen: topckgen@1001B000 {
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+ compatible = "mediatek,mt7986-topckgen";
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+ reg = <0x1001B000 0x1000>;
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+ clock-parent = <&fixed_plls>;
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+ #clock-cells = <1>;
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+ };
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+
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+ infracfg_ao: infracfg_ao@10001000 {
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+ compatible = "mediatek,mt7986-infracfg_ao";
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+ reg = <0x10001000 0x68>;
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+ clock-parent = <&infracfg>;
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+ #clock-cells = <1>;
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+ };
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+
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+ infracfg: infracfg@10001040 {
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+ compatible = "mediatek,mt7986-infracfg";
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+ reg = <0x10001000 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ };
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+
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+ pinctrl: pinctrl@1001f000 {
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+ compatible = "mediatek,mt7986-pinctrl";
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+ reg = <0x1001f000 0x1000>,
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+ <0x11c30000 0x1000>,
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+ <0x11c40000 0x1000>,
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+ <0x11e20000 0x1000>,
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+ <0x11e30000 0x1000>,
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+ <0x11f00000 0x1000>,
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+ <0x11f10000 0x1000>,
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+ <0x1000b000 0x1000>;
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+ reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
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+ "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
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+ "iocfg_tl_base", "eint";
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+ gpio: gpio-controller {
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+ };
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+
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+ pwm: pwm@10048000 {
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+ compatible = "mediatek,mt7986-pwm";
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+ reg = <0x10048000 0x1000>;
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+ #clock-cells = <1>;
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+ #pwm-cells = <2>;
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+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CK_INFRA_PWM>,
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+ <&infracfg_ao CK_INFRA_PWM_BSEL>,
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+ <&infracfg_ao CK_INFRA_PWM1_CK>,
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+ <&infracfg_ao CK_INFRA_PWM2_CK>;
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+ assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
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+ <&infracfg CK_INFRA_PWM_BSEL>,
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+ <&infracfg CK_INFRA_PWM1_SEL>,
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+ <&infracfg CK_INFRA_PWM2_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
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+ <&infracfg CK_INFRA_PWM>,
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+ <&infracfg CK_INFRA_PWM>,
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+ <&infracfg CK_INFRA_PWM>;
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+ clock-names = "top", "main", "pwm1", "pwm2";
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+ status = "disabled";
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+ u-boot,dm-pre-reloc;
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+ };
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+
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+ uart0: serial@11002000 {
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+ compatible = "mediatek,hsuart";
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+ reg = <0x11002000 0x400>;
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
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+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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+ <&infracfg_ao CK_INFRA_UART0_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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+ <&infracfg CK_INFRA_UART>;
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+ mediatek,force-highspeed;
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+ status = "disabled";
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+ u-boot,dm-pre-reloc;
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+ };
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+
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+ uart1: serial@11003000 {
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+ compatible = "mediatek,hsuart";
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+ reg = <0x11003000 0x400>;
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+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
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+ assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
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+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
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+ mediatek,force-highspeed;
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+ status = "disabled";
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+ };
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+
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+ uart2: serial@11004000 {
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+ compatible = "mediatek,hsuart";
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+ reg = <0x11004000 0x400>;
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+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
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+ assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
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+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
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+ mediatek,force-highspeed;
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+ status = "disabled";
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+ };
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+
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+ snand: snand@11005000 {
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+ compatible = "mediatek,mt7986-snand";
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+ reg = <0x11005000 0x1000>,
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+ <0x11006000 0x1000>;
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+ reg-names = "nfi", "ecc";
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+ clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
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+ <&infracfg_ao CK_INFRA_NFI1_CK>,
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+ <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
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+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
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+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
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+ <&topckgen CK_TOP_NFI1X_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
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+ <&topckgen CK_TOP_CB_M_D8>;
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+ status = "disabled";
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+ };
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+
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+ ethsys: syscon@15000000 {
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+ compatible = "mediatek,mt7986-ethsys", "syscon";
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+ reg = <0x15000000 0x1000>;
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+ clock-parent = <&topckgen>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ eth: ethernet@15100000 {
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+ compatible = "mediatek,mt7986-eth", "syscon";
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+ reg = <0x15100000 0x20000>;
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+ resets = <ðsys ETHSYS_FE_RST>;
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+ reset-names = "fe";
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+ mediatek,ethsys = <ðsys>;
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+ mediatek,sgmiisys = <&sgmiisys0>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ sgmiisys0: syscon@10060000 {
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+ compatible = "mediatek,mt7986-sgmiisys", "syscon";
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+ reg = <0x10060000 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ sgmiisys1: syscon@10070000 {
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+ compatible = "mediatek,mt7986-sgmiisys", "syscon";
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+ reg = <0x10070000 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ spi0: spi@1100a000 {
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+ compatible = "mediatek,ipm-spi";
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+ reg = <0x1100a000 0x100>;
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+ clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
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+ <&topckgen CK_TOP_SPI_SEL>;
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+ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
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+ <&infracfg CK_INFRA_SPI0_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
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+ <&topckgen CK_INFRA_ISPI0>;
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+ clock-names = "sel-clk", "spi-clk";
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+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ spi1: spi@1100b000 {
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+ compatible = "mediatek,ipm-spi";
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+ reg = <0x1100b000 0x100>;
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ mmc0: mmc@11230000 {
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+ compatible = "mediatek,mt7986-mmc";
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+ reg = <0x11230000 0x1000>,
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+ <0x11C20000 0x1000>;
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+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CK_TOP_EMMC_416M>,
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+ <&topckgen CK_TOP_EMMC_250M>,
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+ <&infracfg_ao CK_INFRA_MSDC_CK>;
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+ assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
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+ <&topckgen CK_TOP_EMMC_250M_SEL>;
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+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
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+ <&topckgen CK_TOP_NET1_D5_D2>;
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+ clock-names = "source", "hclk", "source_cg";
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+ status = "disabled";
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+ };
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+
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+ xhci: xhci@11200000 {
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+ compatible = "mediatek,mt7986-xhci",
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+ "mediatek,mtk-xhci";
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+ reg = <0x11200000 0x2e00>,
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+ <0x11203e00 0x0100>;
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+ reg-names = "mac", "ippc";
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+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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+ phys = <&u2port0 PHY_TYPE_USB2>,
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+ <&u3port0 PHY_TYPE_USB3>,
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+ <&u2port1 PHY_TYPE_USB2>;
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+ clocks = <&dummy_clk>,
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+ <&dummy_clk>,
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+ <&dummy_clk>,
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+ <&dummy_clk>,
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+ <&dummy_clk>;
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+ clock-names = "sys_ck",
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+ "xhci_ck",
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+ "ref_ck",
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+ "mcu_ck",
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+ "dma_ck";
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+ tpl-support;
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+ status = "okay";
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+ };
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+
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+ usbtphy: usb-phy@11e10000 {
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+ compatible = "mediatek,mt7986",
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+ "mediatek,generic-tphy-v2";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ status = "okay";
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+
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+ u2port0: usb-phy@11e10000 {
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+ reg = <0x11e10000 0x700>;
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+ clocks = <&dummy_clk>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+
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+ u3port0: usb-phy@11e10700 {
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+ reg = <0x11e10700 0x900>;
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+ clocks = <&dummy_clk>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+
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+ u2port1: usb-phy@11e11000 {
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+ reg = <0x11e11000 0x700>;
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+ clocks = <&dummy_clk>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+ };
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+};
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--- a/arch/arm/mach-mediatek/Kconfig
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+++ b/arch/arm/mach-mediatek/Kconfig
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@@ -40,6 +40,14 @@ config TARGET_MT7629
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including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
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switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
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+config TARGET_MT7986
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+ bool "MediaTek MT7986 SoC"
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+ select ARM64
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+ help
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+ The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53.
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+ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
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+ Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
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+
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config TARGET_MT8183
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bool "MediaTek MT8183 SoC"
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select ARM64
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@@ -84,6 +92,7 @@ config SYS_BOARD
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default "mt7622" if TARGET_MT7622
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default "mt7623" if TARGET_MT7623
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default "mt7629" if TARGET_MT7629
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+ default "mt7986" if TARGET_MT7986
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default "mt8183" if TARGET_MT8183
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default "mt8512" if TARGET_MT8512
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default "mt8516" if TARGET_MT8516
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@@ -99,6 +108,7 @@ config SYS_CONFIG_NAME
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default "mt7622" if TARGET_MT7622
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default "mt7623" if TARGET_MT7623
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default "mt7629" if TARGET_MT7629
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+ default "mt7986" if TARGET_MT7986
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default "mt8183" if TARGET_MT8183
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default "mt8512" if TARGET_MT8512
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default "mt8516" if TARGET_MT8516
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@@ -113,6 +123,7 @@ config MTK_BROM_HEADER_INFO
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string
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default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
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default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
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+ default "media=snand;nandinfo=2k+64" if TARGET_MT7986
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default "lk=1" if TARGET_MT7623
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endif
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--- a/arch/arm/mach-mediatek/Makefile
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+++ b/arch/arm/mach-mediatek/Makefile
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@@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
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obj-$(CONFIG_TARGET_MT7622) += mt7622/
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obj-$(CONFIG_TARGET_MT7623) += mt7623/
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obj-$(CONFIG_TARGET_MT7629) += mt7629/
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+obj-$(CONFIG_TARGET_MT7986) += mt7986/
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obj-$(CONFIG_TARGET_MT8183) += mt8183/
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obj-$(CONFIG_TARGET_MT8516) += mt8516/
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obj-$(CONFIG_TARGET_MT8518) += mt8518/
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--- /dev/null
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+++ b/arch/arm/mach-mediatek/mt7986/Makefile
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@@ -0,0 +1,4 @@
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+# SPDX-License-Identifier: GPL-2.0
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+
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+obj-y += init.o
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+obj-y += lowlevel_init.o
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--- /dev/null
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+++ b/arch/arm/mach-mediatek/mt7986/init.c
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@@ -0,0 +1,51 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+#include <init.h>
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+#include <asm/armv8/mmu.h>
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+#include <asm/system.h>
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+#include <asm/global_data.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+int print_cpuinfo(void)
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+{
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+ printf("CPU: MediaTek MT7986\n");
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+ return 0;
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+}
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+
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+int dram_init(void)
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+{
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+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
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+
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+ return 0;
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+}
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+
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+void reset_cpu(ulong addr)
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+{
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+ psci_system_reset();
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+}
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+
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+static struct mm_region mt7986_mem_map[] = {
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+ {
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+ /* DDR */
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+ .virt = 0x40000000UL,
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+ .phys = 0x40000000UL,
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+ .size = 0x80000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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+ }, {
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+ .virt = 0x00000000UL,
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+ .phys = 0x00000000UL,
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+ .size = 0x40000000UL,
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+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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+ PTE_BLOCK_NON_SHARE |
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+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
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+ }, {
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+ 0,
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+ }
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+};
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+
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+struct mm_region *mem_map = mt7986_mem_map;
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--- /dev/null
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+++ b/arch/arm/mach-mediatek/mt7986/lowlevel_init.S
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@@ -0,0 +1,32 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+/*
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+ * Switch from AArch64 EL2 to AArch32 EL2
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+ * @param inputs:
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+ * x0: argument, zero
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+ * x1: machine nr
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+ * x2: fdt address
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+ * x3: input argument
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+ * x4: kernel entry point
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+ * @param outputs for secure firmware:
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+ * x0: function id
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+ * x1: kernel entry point
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+ * x2: machine nr
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+ * x3: fdt address
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+ *
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+ * [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c
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+*/
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+
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+.global armv8_el2_to_aarch32
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+armv8_el2_to_aarch32:
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+ mov x3, x2
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+ mov x2, x1
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+ mov x1, x4
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+ mov x4, #0
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+ ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */
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+ SMC #0
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+ ret
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