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d442790bbf
Currently, IPQ807x is using CPUFreq NVMEM for dealing with different SoC SKU-s having different frequency limits, and we are keeping the patches for it in ipq807x target. However, we managed to upstream a big cleanup of the driver in order to make it possible for other SMEM based targets to be added to CPUFreq NVMEM. IPQ806x will be using CPUFreq NVMEM and depends on these changes as well, so lets put them in generic backport to avoid code duplication. This replaces the older patches in ipq807x. Signed-off-by: Robert Marko <robimarko@gmail.com>
172 lines
4.3 KiB
Diff
172 lines
4.3 KiB
Diff
From 7cbff3c3f867ff3b24de674f44ca03f54e416a37 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 31 Dec 2022 00:27:42 +0100
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Subject: [PATCH] soc: qcom: socinfo: move SMEM item struct and defines to a
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header
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Move SMEM item struct and related defines to a header in order to be able
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to reuse them in the Qualcomm NVMEM CPUFreq driver instead of duplicating
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them.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230526204802.3081168-1-robimarko@gmail.com
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---
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drivers/soc/qcom/socinfo.c | 58 +--------------------------
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include/linux/soc/qcom/socinfo.h | 67 ++++++++++++++++++++++++++++++++
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2 files changed, 68 insertions(+), 57 deletions(-)
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create mode 100644 include/linux/soc/qcom/socinfo.h
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--- a/drivers/soc/qcom/socinfo.c
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+++ b/drivers/soc/qcom/socinfo.c
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@@ -11,6 +11,7 @@
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/soc/qcom/smem.h>
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+#include <linux/soc/qcom/socinfo.h>
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#include <linux/string.h>
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#include <linux/sys_soc.h>
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#include <linux/types.h>
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@@ -25,15 +26,6 @@
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#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
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#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
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-#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
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-#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
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-
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-/*
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- * SMEM item id, used to acquire handles to respective
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- * SMEM region.
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- */
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-#define SMEM_HW_SW_BUILD_ID 137
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-
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#ifdef CONFIG_DEBUG_FS
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#define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32
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#define SMEM_IMAGE_VERSION_SIZE 4096
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@@ -116,54 +108,6 @@ static const char *const pmic_models[] =
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};
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#endif /* CONFIG_DEBUG_FS */
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-/* Socinfo SMEM item structure */
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-struct socinfo {
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- __le32 fmt;
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- __le32 id;
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- __le32 ver;
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- char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
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- /* Version 2 */
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- __le32 raw_id;
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- __le32 raw_ver;
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- /* Version 3 */
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- __le32 hw_plat;
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- /* Version 4 */
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- __le32 plat_ver;
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- /* Version 5 */
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- __le32 accessory_chip;
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- /* Version 6 */
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- __le32 hw_plat_subtype;
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- /* Version 7 */
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- __le32 pmic_model;
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- __le32 pmic_die_rev;
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- /* Version 8 */
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- __le32 pmic_model_1;
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- __le32 pmic_die_rev_1;
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- __le32 pmic_model_2;
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- __le32 pmic_die_rev_2;
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- /* Version 9 */
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- __le32 foundry_id;
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- /* Version 10 */
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- __le32 serial_num;
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- /* Version 11 */
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- __le32 num_pmics;
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- __le32 pmic_array_offset;
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- /* Version 12 */
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- __le32 chip_family;
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- __le32 raw_device_family;
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- __le32 raw_device_num;
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- /* Version 13 */
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- __le32 nproduct_id;
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- char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
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- /* Version 14 */
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- __le32 num_clusters;
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- __le32 ncluster_array_offset;
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- __le32 num_defective_parts;
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- __le32 ndefective_parts_array_offset;
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- /* Version 15 */
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- __le32 nmodem_supported;
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-};
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-
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#ifdef CONFIG_DEBUG_FS
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struct socinfo_params {
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u32 raw_device_family;
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--- /dev/null
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+++ b/include/linux/soc/qcom/socinfo.h
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@@ -0,0 +1,67 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2017-2019, Linaro Ltd.
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+ */
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+
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+#ifndef __QCOM_SOCINFO_H__
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+#define __QCOM_SOCINFO_H__
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+
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+/*
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+ * SMEM item id, used to acquire handles to respective
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+ * SMEM region.
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+ */
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+#define SMEM_HW_SW_BUILD_ID 137
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+
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+#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
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+#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
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+
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+/* Socinfo SMEM item structure */
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+struct socinfo {
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+ __le32 fmt;
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+ __le32 id;
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+ __le32 ver;
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+ char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
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+ /* Version 2 */
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+ __le32 raw_id;
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+ __le32 raw_ver;
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+ /* Version 3 */
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+ __le32 hw_plat;
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+ /* Version 4 */
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+ __le32 plat_ver;
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+ /* Version 5 */
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+ __le32 accessory_chip;
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+ /* Version 6 */
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+ __le32 hw_plat_subtype;
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+ /* Version 7 */
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+ __le32 pmic_model;
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+ __le32 pmic_die_rev;
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+ /* Version 8 */
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+ __le32 pmic_model_1;
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+ __le32 pmic_die_rev_1;
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+ __le32 pmic_model_2;
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+ __le32 pmic_die_rev_2;
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+ /* Version 9 */
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+ __le32 foundry_id;
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+ /* Version 10 */
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+ __le32 serial_num;
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+ /* Version 11 */
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+ __le32 num_pmics;
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+ __le32 pmic_array_offset;
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+ /* Version 12 */
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+ __le32 chip_family;
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+ __le32 raw_device_family;
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+ __le32 raw_device_num;
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+ /* Version 13 */
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+ __le32 nproduct_id;
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+ char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
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+ /* Version 14 */
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+ __le32 num_clusters;
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+ __le32 ncluster_array_offset;
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+ __le32 num_defective_parts;
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+ __le32 ndefective_parts_array_offset;
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+ /* Version 15 */
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+ __le32 nmodem_supported;
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+};
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+
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+#endif
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