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5c786dcb2b
Add downstream DT property to setup the PHY LEDs of the MaxLinear
GPY211 PHY in such way that the VDD of the LED is driven by the SoC
pin rather than the GND (which is the default).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 90fbec89be)
[removed patches for kernel 6.1]
Signed-off-by: Tom Herbers <mail@tomherbers.de>
106 lines
2.8 KiB
Diff
106 lines
2.8 KiB
Diff
From 94b90966095f3fa625897e8f53d215882f6e19b3 Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Sat, 11 Mar 2023 17:00:01 +0100
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Subject: [PATCH] mxl-gpy: control LED reg from DT
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Add dynamic configuration for the LED control registers on MXL PHYs.
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This patch has been tested with MaxLinear GPY211C. It is unlikely to be
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accepted upstream, as upstream plans on integrating their own framework
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for handling these LEDs.
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For the time being, use this hack to configure PHY driven device-LEDs to
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show the correct state.
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A possible alternative might be to expose the LEDs using the kernel LED
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framework and bind it to the netdevice. This might also be upstreamable,
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although it is a considerable extra amount of work.
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Signed-off-by: David Bauer <mail@david-bauer.net>
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---
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drivers/net/phy/mxl-gpy.c | 37 ++++++++++++++++++++++++++++++++++++-
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1 file changed, 36 insertions(+), 1 deletion(-)
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--- a/drivers/net/phy/mxl-gpy.c
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+++ b/drivers/net/phy/mxl-gpy.c
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@@ -8,6 +8,7 @@
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#include <linux/module.h>
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#include <linux/bitfield.h>
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+#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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@@ -30,6 +31,7 @@
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#define PHY_MIISTAT 0x18 /* MII state */
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#define PHY_IMASK 0x19 /* interrupt mask */
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#define PHY_ISTAT 0x1A /* interrupt status */
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+#define PHY_LED 0x1B /* LED control */
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#define PHY_FWV 0x1E /* firmware version */
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#define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
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@@ -53,10 +55,15 @@
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PHY_IMASK_ADSC | \
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PHY_IMASK_ANC)
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+#define PHY_LED_NUM_LEDS 4
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+
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#define PHY_FWV_REL_MASK BIT(15)
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#define PHY_FWV_TYPE_MASK GENMASK(11, 8)
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#define PHY_FWV_MINOR_MASK GENMASK(7, 0)
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+/* LED */
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+#define VSPEC1_LED(x) (0x1 + x)
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+
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/* SGMII */
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#define VSPEC1_SGMII_CTRL 0x08
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#define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
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@@ -80,6 +87,35 @@ static const struct {
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{9, 0x73},
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};
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+static int gpy_led_write(struct phy_device *phydev)
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+{
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+ struct device_node *node = phydev->mdio.dev.of_node;
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+ u32 led_regs[PHY_LED_NUM_LEDS];
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+ int i, ret;
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+ u16 val = 0xff00;
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+
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+ if (!IS_ENABLED(CONFIG_OF_MDIO))
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+ return 0;
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+
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+ if (of_property_read_u32_array(node, "mxl,led-config", led_regs, PHY_LED_NUM_LEDS))
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+ return 0;
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+
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+ if (of_property_read_bool(node, "mxl,led-drive-vdd"))
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+ val &= 0x0fff;
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+
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+ /* Enable LED function handling on all ports*/
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+ phy_write(phydev, PHY_LED, val);
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+
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+ /* Write LED register values */
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+ for (i = 0; i < PHY_LED_NUM_LEDS; i++) {
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+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(i), (u16)led_regs[i]);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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static int gpy_config_init(struct phy_device *phydev)
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{
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int ret;
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@@ -91,7 +127,10 @@ static int gpy_config_init(struct phy_de
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/* Clear all pending interrupts */
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ret = phy_read(phydev, PHY_ISTAT);
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- return ret < 0 ? ret : 0;
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+ if (ret < 0)
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+ return ret;
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+
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+ return gpy_led_write(phydev);
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}
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static int gpy_probe(struct phy_device *phydev)
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