Robert Marko 845caa8d46 qualcommax: 301w: correct AQR reset GPIO-s ... It seems that the reset GPIO-s defined for the two AQR PHY-s are actually reversed. Manually testing confirmed that GPIO44 is actually reset GPIO of AQR at 0, while GPIO59 is reset of AQR at 8: root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 44=0 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 44=1 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 59=0 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down root@OpenWrt:~# gpioset gpiochip0 59=1 root@OpenWrt:~# mdio 9* DEV PHY-ID LINK 0x00 0x00000000 down 0x08 0x00000000 down 0x10 0x004dd0b1 down 0x11 0x004dd0b1 down 0x12 0x004dd0b1 down 0x13 0x004dd0b1 up 0x14 0x004dd0b1 down 0x15 0x04820a05 down Signed-off-by: Robert Marko <robimarko@gmail.com>		2024-01-26 15:30:02 +01:00
..
imagebuilder	imagebuilder: copy from buildroot only target/linux/generic and target/linux/<target> to reduce the size	2024-01-15 16:49:12 +01:00
linux	qualcommax: 301w: correct AQR reset GPIO-s	2024-01-26 15:30:02 +01:00
llvm-bpf
sdk	tools: add ledumon and ledhwbmon packages	2023-12-12 19:35:03 +01:00
toolchain	treewide: add ORIG_PATH variable	2023-06-05 08:31:47 +02:00
Config.in	generic: groundwork for RISC-V	2023-05-28 13:19:10 +02:00
Makefile