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f1525e785e
Backport below changes for GigaDevice GD25Q256 support from v4.15: e27072851bf7 mtd: spi-nor: add a quad_enable callback in struct flash_info 65153846b18c mtd: spi-nor: add support for GD25Q256 This chip is used on newer Quad-E4G boards. Before: [ 2.366493] m25p80 spi0.0: unrecognized JEDEC id bytes: c8, 40, 19 [ 2.372853] m25p80: probe of spi0.0 failed with error -2 After: [ 2.371722] m25p80 spi0.0: gd25q256 (32768 Kbytes) [ 2.376694] 5 fixed-partitions partitions found on MTD device spi0.0 [ 2.383043] Creating 5 MTD partitions on "spi0.0": [ 2.387824] 0x000000000000-0x000000030000 : "u-boot" [ 2.394138] 0x000000030000-0x000000031000 : "u-boot-env" [ 2.400608] 0x000000031000-0x000000040000 : "config" [ 2.406830] 0x000000040000-0x000000050000 : "factory" [ 2.413169] 0x000000050000-0x000002000000 : "firmware" Signed-off-by: Kuan-Yi Li <kyli@abysm.org>
35 lines
1.1 KiB
Diff
35 lines
1.1 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Subject: [PATCH] mtd: spi-nor: detect JEDEC incompatible w25q128 using 0x90
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command
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Some w25q128 chipsets don't support RDID (0x9f) command, they reply with
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0xff-s only. To suppose such flashes fallback to the 0x90 command.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -1237,6 +1237,18 @@ static const struct flash_info *spi_nor_
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}
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dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
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id[0], id[1], id[2]);
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+
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+ tmp = nor->read_reg(nor, 0x90, id, SPI_NOR_MAX_ID_LEN);
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+ if (tmp < 0) {
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+ dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
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+ return ERR_PTR(tmp);
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+ }
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+ dev_info(nor->dev, "using Read Manufacturer / Device ID command (0x%02x) returned %02x %02x\n",
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+ 0x90, id[0x03], id[0x04]);
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+ if (id[0x03] == 0xef && id[0x04] == 0x17) {
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+ return spi_nor_match_id("w25q128");
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+ }
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+
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return ERR_PTR(-ENODEV);
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}
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