mirror of
https://github.com/openwrt/openwrt.git
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662d1f9f8d
Removed upstreamed:
generic/backport-5.10/350-v5.18-MIPS-pgalloc-fix-memory-leak-caused-by-pgd_free.patch
generic/pending-5.10/850-0014-PCI-aardvark-Fix-reading-PCI_EXP_RTSTA_PME-bit-on-em.patch
ipq40xx/patches-5.10/105-ipq40xx-fix-sleep-clock.patch
All patches automatically rebased.
Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200
Compile-/run-tested: ath79/generic (Archer C7 v2).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
[rebased in 22.03 tree]
Signed-off-by: John Audia <graysky@archlinux.us>
(cherry picked from commit b92ec82235)
174 lines
5.7 KiB
Diff
174 lines
5.7 KiB
Diff
From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Tue, 19 Jan 2021 14:59:25 +0200
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Subject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add
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clocksource suspend/resume
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Add suspend/resume support for clocksource timer.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Link: https://lore.kernel.org/r/1611061165-30180-1-git-send-email-claudiu.beznea@microchip.com
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---
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drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++----
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1 file changed, 71 insertions(+), 15 deletions(-)
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--- a/drivers/clocksource/timer-microchip-pit64b.c
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+++ b/drivers/clocksource/timer-microchip-pit64b.c
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@@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt {
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struct clock_event_device clkevt;
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};
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-#define to_mchp_pit64b_timer(x) \
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+#define clkevt_to_mchp_pit64b_timer(x) \
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((struct mchp_pit64b_timer *)container_of(x,\
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struct mchp_pit64b_clkevt, clkevt))
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+/**
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+ * mchp_pit64b_clksrc - PIT64B clocksource data structure
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+ * @timer: PIT64B timer
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+ * @clksrc: clocksource
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+ */
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+struct mchp_pit64b_clksrc {
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+ struct mchp_pit64b_timer timer;
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+ struct clocksource clksrc;
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+};
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+
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+#define clksrc_to_mchp_pit64b_timer(x) \
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+ ((struct mchp_pit64b_timer *)container_of(x,\
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+ struct mchp_pit64b_clksrc, clksrc))
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+
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/* Base address for clocksource timer. */
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static void __iomem *mchp_pit64b_cs_base;
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/* Default cycles for clockevent timer. */
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@@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(str
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writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
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}
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+static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
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+{
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+ writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
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+ if (timer->mode & MCHP_PIT64B_MR_SGCLK)
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+ clk_disable_unprepare(timer->gclk);
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+ clk_disable_unprepare(timer->pclk);
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+}
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+
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+static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
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+{
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+ clk_prepare_enable(timer->pclk);
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+ if (timer->mode & MCHP_PIT64B_MR_SGCLK)
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+ clk_prepare_enable(timer->gclk);
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+}
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+
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+static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
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+{
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+ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
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+
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+ mchp_pit64b_suspend(timer);
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+}
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+
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+static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
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+{
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+ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
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+
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+ mchp_pit64b_resume(timer);
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+ mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
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+}
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+
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static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
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{
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return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
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@@ -128,7 +172,7 @@ static u64 notrace mchp_pit64b_sched_rea
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static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
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{
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- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
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+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
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writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
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@@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(s
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static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
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{
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- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
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+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
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mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
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MCHP_PIT64B_IER_PERIOD);
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@@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_period
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static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
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struct clock_event_device *cedev)
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{
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- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
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+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
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mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
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MCHP_PIT64B_IER_PERIOD);
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@@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_e
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static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
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{
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- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
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+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
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- writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
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- if (timer->mode & MCHP_PIT64B_MR_SGCLK)
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- clk_disable_unprepare(timer->gclk);
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- clk_disable_unprepare(timer->pclk);
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+ mchp_pit64b_suspend(timer);
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}
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static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
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{
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- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
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+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
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- clk_prepare_enable(timer->pclk);
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- if (timer->mode & MCHP_PIT64B_MR_SGCLK)
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- clk_prepare_enable(timer->gclk);
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+ mchp_pit64b_resume(timer);
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}
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static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
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@@ -296,20 +335,37 @@ done:
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static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
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u32 clk_rate)
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{
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+ struct mchp_pit64b_clksrc *cs;
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int ret;
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+ cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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+ if (!cs)
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+ return -ENOMEM;
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+
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mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
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mchp_pit64b_cs_base = timer->base;
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- ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
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- 210, 64, mchp_pit64b_clksrc_read);
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+ cs->timer.base = timer->base;
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+ cs->timer.pclk = timer->pclk;
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+ cs->timer.gclk = timer->gclk;
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+ cs->timer.mode = timer->mode;
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+ cs->clksrc.name = MCHP_PIT64B_NAME;
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+ cs->clksrc.mask = CLOCKSOURCE_MASK(64);
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+ cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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+ cs->clksrc.rating = 210;
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+ cs->clksrc.read = mchp_pit64b_clksrc_read;
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+ cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
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+ cs->clksrc.resume = mchp_pit64b_clksrc_resume;
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+
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+ ret = clocksource_register_hz(&cs->clksrc, clk_rate);
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if (ret) {
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pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
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/* Stop timer. */
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writel_relaxed(MCHP_PIT64B_CR_SWRST,
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timer->base + MCHP_PIT64B_CR);
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+ kfree(cs);
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return ret;
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}
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