mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-19 13:48:06 +00:00
8b66f1a06d
For all boards currently working with the mt7530 DSA driver we can be sure that the address of the switch on the MDIO bus is 31 -- simply because that address is hard-coded in the driver and the address from the Device Tree is being ignore. An upcoming patch will add support for MT753x ICs which are programmed to addresses different from 0x1f using bootstrap pins. As a result the address from the Device Tree will then be taken into account, which will break currently working boards which got the address set to anything else than 31. While at it also unify the syntax in Device Tree to always us a decimal value for the 'reg' property. * mt7622-buffalo-wsr-3200ax4s.dts Cosmetic change 'reg = <0x1f>' -> 'reg = <31>' * mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi Wrong address: 0 -> 31 * mt7622-elecom-wrc-x3200gst3.dts Wrong address: 0 -> 31 * mt7622-linksys-e8450.dtsi Wrong address: 0 -> 31 * mt7622-ruijie-rg-ew3200.dtsi Wrong address: 0 -> 31 * mt7622-xiaomi-redmi-router-ax6s.dts Wrong address: 0 -> 31 * mt7629-iptime-a6004mx.dts Wrong address: 2 -> 31 * mt7981b-zbtlink-zbt-z8102ax.dts Cosmetic change 'reg = <0x1f>' -> 'reg = <31>' Signed-off-by: Daniel Golle <daniel@makrotopia.org>
299 lines
5.0 KiB
Plaintext
299 lines
5.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
|
|
/dts-v1/;
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/leds/common.h>
|
|
#include "mt7629.dtsi"
|
|
|
|
/ {
|
|
model = "ipTIME A6004MX";
|
|
compatible = "iptime,a6004mx", "mediatek,mt7629";
|
|
|
|
aliases {
|
|
led-boot = &led_cpu;
|
|
led-failsafe = &led_cpu;
|
|
led-running = &led_cpu;
|
|
led-upgrade = &led_cpu;
|
|
serial0 = &uart0;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
bootargs-override = "console=ttyS0,115200n8";
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_cpu: cpu {
|
|
function = LED_FUNCTION_CPU;
|
|
color = <LED_COLOR_ID_ORANGE>;
|
|
gpios = <&pio 57 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wlan5g {
|
|
label = "orange:wlan5g";
|
|
gpios = <&pio 22 GPIO_ACTIVE_LOW>;
|
|
// linux,default-trigger = "phy0radio";
|
|
};
|
|
|
|
wlan2g {
|
|
label = "orange:wlan2g";
|
|
gpios = <&pio 21 GPIO_ACTIVE_LOW>;
|
|
// linux,default-trigger = "phy1radio";
|
|
};
|
|
|
|
wan {
|
|
function = LED_FUNCTION_WAN;
|
|
color = <LED_COLOR_ID_ORANGE>;
|
|
gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "factory";
|
|
linux,code = <KEY_RESTART>;
|
|
gpios = <&pio 60 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wps {
|
|
label = "wps";
|
|
linux,code = <KEY_WPS_BUTTON>;
|
|
gpios = <&pio 58 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x40000000 0x10000000>;
|
|
};
|
|
|
|
reg_3p3v: regulator-3p3v {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "fixed-3.3V";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
reg_5v: regulator-5v {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "fixed-5V";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|
|
ð {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <ð_pins>;
|
|
pinctrl-1 = <&ephy_leds_pins>;
|
|
status = "okay";
|
|
|
|
gmac0: mac@0 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <0>;
|
|
phy-mode = "2500base-x";
|
|
nvmem-cells = <&macaddr_factory_4 3>;
|
|
nvmem-cell-names = "mac-address";
|
|
|
|
fixed-link {
|
|
speed = <2500>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
};
|
|
|
|
gmac1: mac@1 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <1>;
|
|
phy-mode = "gmii";
|
|
phy-handle = <&phy0>;
|
|
nvmem-cells = <&macaddr_factory_4 1>;
|
|
nvmem-cell-names = "mac-address";
|
|
};
|
|
|
|
mdio: mdio-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
switch@1f {
|
|
compatible = "mediatek,mt7531";
|
|
reg = <31>;
|
|
reset-gpios = <&pio 28 0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
label = "lan1";
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
label = "lan2";
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
label = "lan3";
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
label = "lan4";
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
ethernet = <&gmac0>;
|
|
phy-mode = "2500base-x";
|
|
|
|
fixed-link {
|
|
speed = <2500>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&bch {
|
|
status = "okay";
|
|
};
|
|
|
|
&snfi {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&serial_nand_pins>;
|
|
status = "okay";
|
|
flash@0 {
|
|
compatible = "spi-nand";
|
|
reg = <0>;
|
|
spi-tx-bus-width = <4>;
|
|
spi-rx-bus-width = <4>;
|
|
nand-ecc-engine = <&snfi>;
|
|
mediatek,bmt-v2;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "Bootloader";
|
|
reg = <0x0 0x100000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@100000 {
|
|
label = "Config";
|
|
reg = <0x100000 0x40000>;
|
|
};
|
|
|
|
partition@140000 {
|
|
label = "factory";
|
|
reg = <0x140000 0x80000>;
|
|
read-only;
|
|
|
|
nvmem-layout {
|
|
compatible = "fixed-layout";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
macaddr_factory_4: macaddr@4 {
|
|
compatible = "mac-base";
|
|
reg = <0x4 0x6>;
|
|
#nvmem-cell-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
partition@1c0000 {
|
|
label = "firmware";
|
|
reg = <0x1c0000 0x7400000>;
|
|
compatible = "denx,fit";
|
|
openwrt,fit-offset = <0x800>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pio {
|
|
eth_pins: eth-pins {
|
|
mux {
|
|
function = "eth";
|
|
groups = "mdc_mdio";
|
|
};
|
|
};
|
|
|
|
ephy_leds_pins: ephy-leds-pins {
|
|
mux {
|
|
function = "led";
|
|
groups = "ephy_leds";
|
|
};
|
|
};
|
|
|
|
/* Serial NAND is shared pin with SPI-NOR */
|
|
serial_nand_pins: serial-nand-pins {
|
|
mux {
|
|
function = "flash";
|
|
groups = "snfi";
|
|
};
|
|
};
|
|
|
|
uart0_pins: uart0-pins {
|
|
mux {
|
|
function = "uart";
|
|
groups = "uart0_txd_rxd" ;
|
|
};
|
|
};
|
|
|
|
watchdog_pins: watchdog-pins {
|
|
mux {
|
|
function = "watchdog";
|
|
groups = "watchdog";
|
|
};
|
|
};
|
|
};
|
|
|
|
&ssusb {
|
|
vusb33-supply = <®_3p3v>;
|
|
vbus-supply = <®_5v>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&watchdog {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&watchdog_pins>;
|
|
status = "okay";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <GIC_SPI 0x80 IRQ_TYPE_EDGE_FALLING>;
|
|
};
|