mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
8299d1f057
Rebased RPi foundation patches on linux 5.10.59, removed applied and reverted patches, wireless patches and defconfig patches. bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 4B v1.1 4G bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
56 lines
2.0 KiB
Diff
56 lines
2.0 KiB
Diff
From acc8ac41d15594d4f735531c89bbeb03d85c344d Mon Sep 17 00:00:00 2001
|
|
From: Maxime Ripard <maxime@cerno.tech>
|
|
Date: Thu, 8 Oct 2020 16:06:08 +0200
|
|
Subject: [PATCH] drm/vc4: hdmi: Properly compute the BVB clock rate
|
|
|
|
The BVB clock rate computation doesn't take into account a mode clock of
|
|
594MHz that we're going to need to support 4k60.
|
|
|
|
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
|
|
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
|
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_hdmi.c | 17 +++++++++--------
|
|
1 file changed, 9 insertions(+), 8 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
@@ -92,7 +92,6 @@
|
|
# define VC4_HD_M_ENABLE BIT(0)
|
|
|
|
#define CEC_CLOCK_FREQ 40000
|
|
-#define VC4_HSM_MID_CLOCK 149985000
|
|
|
|
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
|
|
{
|
|
@@ -813,7 +812,7 @@ static void vc4_hdmi_encoder_pre_crtc_co
|
|
conn_state_to_vc4_hdmi_conn_state(conn_state);
|
|
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
|
|
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
|
|
- unsigned long pixel_rate, hsm_rate;
|
|
+ unsigned long bvb_rate, pixel_rate, hsm_rate;
|
|
int ret;
|
|
|
|
ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
|
|
@@ -862,12 +861,14 @@ static void vc4_hdmi_encoder_pre_crtc_co
|
|
|
|
vc4_hdmi_cec_update_clk_div(vc4_hdmi);
|
|
|
|
- /*
|
|
- * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
|
|
- * at 300MHz.
|
|
- */
|
|
- vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,
|
|
- (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
|
|
+ if (pixel_rate > 297000000)
|
|
+ bvb_rate = 300000000;
|
|
+ else if (pixel_rate > 148500000)
|
|
+ bvb_rate = 150000000;
|
|
+ else
|
|
+ bvb_rate = 75000000;
|
|
+
|
|
+ vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock, bvb_rate);
|
|
if (IS_ERR(vc4_hdmi->bvb_req)) {
|
|
DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req));
|
|
clk_request_done(vc4_hdmi->hsm_req);
|