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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
From 2b0fe9137aa32d7fc367bf3a1cef4fa97ece6d58 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Tue, 23 Aug 2022 22:43:51 +0200
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Subject: [PATCH] phy: qcom-qmp-pcie: make pipe clock rate configurable
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IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
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like every other PCIe QMP PHY does, so make it configurable as part of the
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qmp_phy_cfg.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++--
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1 file changed, 12 insertions(+), 2 deletions(-)
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--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
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+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
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@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg {
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/* true, if PHY has secondary tx/rx lanes to be configured */
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bool is_dual_lane_phy;
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+ /* QMP PHY pipe clock interface rate */
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+ unsigned long pipe_clock_rate;
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+
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/* true, if PCS block has no separate SW_RESET register */
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bool no_pcs_sw_reset;
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};
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@@ -5138,8 +5141,15 @@ static int phy_pipe_clk_register(struct
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init.ops = &clk_fixed_rate_ops;
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- /* controllers using QMP phys use 125MHz pipe clock interface */
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- fixed->fixed_rate = 125000000;
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+ /*
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+ * Controllers using QMP PHY-s use 125MHz pipe clock interface
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+ * unless other frequency is specified in the PHY config.
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+ */
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+ if (qmp->phys[0]->cfg->pipe_clock_rate)
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+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
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+ else
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+ fixed->fixed_rate = 125000000;
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+
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fixed->hw.init = &init;
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ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
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