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2c363a070e
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.75 Removed upstreamed: generic/hack-6.1/321-powerpc_crtsavres_prereq.patch[1] generic/pending-6.1/540-ksmbd-only-v2-leases-handle-the-directory.patch[2] Rebased: bcm27xx/patches-6.1/950-0670-fbdev-Don-t-cancel-deferred-work-if-pagelist-empty.patch[3] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.75&id=16b88e68b85d5520c28498bb847358ff6300cb90 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/fs/smb?h=v6.1.75&id=c866866c795296d3637ab0d48a3d8a3ef5d6f4a3 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.75&id=81f444f22816a82ada2cc787a2845cffc8c584a6 Build system: x86/64 Build-tested: x86/64/AMD Cezanne Run-tested: x86/64/AMD Cezanne Signed-off-by: John Audia <therealgraysky@proton.me>
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From: qizhong cheng <qizhong.cheng@mediatek.com>
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Date: Mon, 27 Dec 2021 21:31:10 +0800
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Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
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stabilize
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
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2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
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be delayed 100ms (TPVPERL) for the power and clock to become stable.
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Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
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Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Acked-by: Pali Rohár <pali@kernel.org>
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---
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--- a/drivers/pci/controller/pcie-mediatek.c
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+++ b/drivers/pci/controller/pcie-mediatek.c
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@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
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*/
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msleep(100);
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+ /*
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+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
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+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
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+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
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+ */
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+ msleep(100);
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+
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/* De-assert PHY, PE, PIPE, MAC and configuration reset */
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val = readl(port->base + PCIE_RST_CTRL);
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val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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