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d4b4bc98bb
Replace clock drivers for MT7988 with backported upstream commits. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
108 lines
3.3 KiB
Diff
108 lines
3.3 KiB
Diff
From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Sun, 19 Mar 2023 12:56:52 +0000
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Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT
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schema
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Convert mediatek,sgmiiisys bindings to DT schema format.
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Add maintainer Matthias Brugger, no maintainers were listed in the
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original documentation.
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As this node is also referenced by the Ethernet controller and used
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as SGMII PCS add this fact to the description.
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Move the file to Documentation/devicetree/bindings/net/pcs/ which seems
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more appropriate given that the great majority of registers are related
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to SGMII PCS functionality and only one register represents clock bits.
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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.../arm/mediatek/mediatek,sgmiisys.txt | 27 ----------
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.../bindings/net/pcs/mediatek,sgmiisys.yaml | 49 +++++++++++++++++++
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2 files changed, 49 insertions(+), 27 deletions(-)
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delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
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create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
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+++ /dev/null
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@@ -1,27 +0,0 @@
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-MediaTek SGMIISYS controller
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-============================
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-
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-The MediaTek SGMIISYS controller provides various clocks to the system.
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-
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-Required Properties:
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-
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-- compatible: Should be:
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- - "mediatek,mt7622-sgmiisys", "syscon"
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- - "mediatek,mt7629-sgmiisys", "syscon"
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- - "mediatek,mt7981-sgmiisys_0", "syscon"
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- - "mediatek,mt7981-sgmiisys_1", "syscon"
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- - "mediatek,mt7986-sgmiisys_0", "syscon"
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- - "mediatek,mt7986-sgmiisys_1", "syscon"
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-- #clock-cells: Must be 1
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-
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-The SGMIISYS controller uses the common clk binding from
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-Documentation/devicetree/bindings/clock/clock-bindings.txt
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-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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-
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-Example:
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-
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-sgmiisys: sgmiisys@1b128000 {
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- compatible = "mediatek,mt7622-sgmiisys", "syscon";
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- reg = <0 0x1b128000 0 0x1000>;
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- #clock-cells = <1>;
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-};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
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@@ -0,0 +1,49 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MediaTek SGMIISYS Controller
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+
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+maintainers:
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+ - Matthias Brugger <matthias.bgg@gmail.com>
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+
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+description:
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+ The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
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+ to the ethernet subsystem to which it is attached.
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+
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+properties:
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+ compatible:
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+ items:
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+ - enum:
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+ - mediatek,mt7622-sgmiisys
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+ - mediatek,mt7629-sgmiisys
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+ - mediatek,mt7986-sgmiisys_0
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+ - mediatek,mt7986-sgmiisys_1
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+ - const: syscon
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+
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+ reg:
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+ maxItems: 1
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+
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+ '#clock-cells':
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - '#clock-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ sgmiisys: syscon@1b128000 {
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+ compatible = "mediatek,mt7622-sgmiisys", "syscon";
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+ reg = <0 0x1b128000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+ };
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