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ab7cabd09d
Compile-tested on: ramips/mt7621, x86/64. Run-tested on: ramips/mt7621. Signed-off-by: Stijn Segers <foss@volatilesystems.org>
131 lines
3.3 KiB
Diff
131 lines
3.3 KiB
Diff
From 9c76dd09d27dff05207241aa67a2c6054d057b32 Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Thu, 28 Dec 2017 10:30:32 +0800
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Subject: [PATCH 210/224] arm64: dts: mt7622: add clock controller device nodes
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Add clock controller nodes for MT7622 and include header for topckgen,
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infracfg, pericfg, apmixedsys, ethsys, sgmiisys, pciesys and ssusbsys
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for those devices nodes to be added afterwards.
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In addition, provides an oscillator node for the source of PLLs and dummy
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clock for PWARP to complement missing support of clock gate for the
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wrapper circuit in the driver.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Cc: Stephen Boyd <sboyd@codeaurora.org>
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---
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 76 ++++++++++++++++++++++++++++++++
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1 file changed, 76 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -8,6 +8,8 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/mt7622-clk.h>
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+#include <dt-bindings/reset/mt7622-reset.h>
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/ {
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compatible = "mediatek,mt7622";
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@@ -48,6 +50,19 @@
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clock-frequency = <280000000>;
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};
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+ pwrap_clk: dummy40m {
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+ compatible = "fixed-clock";
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+ clock-frequency = <40000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ clk25m: oscillator {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <25000000>;
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+ clock-output-names = "clkxtal";
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+ };
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+
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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@@ -78,6 +93,22 @@
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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+ infracfg: infracfg@10000000 {
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+ compatible = "mediatek,mt7622-infracfg",
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+ "syscon";
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+ reg = <0 0x10000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ pericfg: pericfg@10002000 {
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+ compatible = "mediatek,mt7622-pericfg",
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+ "syscon";
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+ reg = <0 0x10002000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,mt7622-sysirq",
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"mediatek,mt6577-sysirq";
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@@ -87,6 +118,20 @@
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reg = <0 0x10200620 0 0x20>;
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};
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+ apmixedsys: apmixedsys@10209000 {
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+ compatible = "mediatek,mt7622-apmixedsys",
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+ "syscon";
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+ reg = <0 0x10209000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ topckgen: topckgen@10210000 {
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+ compatible = "mediatek,mt7622-topckgen",
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+ "syscon";
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+ reg = <0 0x10210000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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@@ -107,4 +152,35 @@
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clock-names = "baud", "bus";
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status = "disabled";
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};
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+
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+ ssusbsys: ssusbsys@1a000000 {
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+ compatible = "mediatek,mt7622-ssusbsys",
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+ "syscon";
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+ reg = <0 0x1a000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ pciesys: pciesys@1a100800 {
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+ compatible = "mediatek,mt7622-pciesys",
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+ "syscon";
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+ reg = <0 0x1a100800 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ ethsys: syscon@1b000000 {
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+ compatible = "mediatek,mt7622-ethsys",
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+ "syscon";
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+ reg = <0 0x1b000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ sgmiisys: sgmiisys@1b128000 {
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+ compatible = "mediatek,mt7622-sgmiisys",
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+ "syscon";
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+ reg = <0 0x1b128000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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};
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