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efb375b579
Refresh patches Fixes: CVE-2017-5754 aka Meltdown Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> [fix typo in commit msg, conflict after 4.14 bump] Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
125 lines
3.9 KiB
Diff
125 lines
3.9 KiB
Diff
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Date: Wed, 9 Dec 2015 18:23:51 +0100
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Subject: [PATCH] net: mvneta: Configure XPS support
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With this patch each CPU is associated with its own set of TX queues.
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It also setup the XPS with an initial configuration which set the
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affinity matching the hardware configuration.
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Suggested-by: Arnd Bergmann <arnd@arndb.de>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/drivers/net/ethernet/marvell/mvneta.c
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+++ b/drivers/net/ethernet/marvell/mvneta.c
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@@ -111,6 +111,7 @@
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#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
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#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
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#define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
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+#define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
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#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
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/* Exception Interrupt Port/Queue Cause register
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@@ -514,6 +515,9 @@ struct mvneta_tx_queue {
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/* DMA address of TSO headers */
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dma_addr_t tso_hdrs_phys;
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+
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+ /* Affinity mask for CPUs*/
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+ cpumask_t affinity_mask;
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};
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struct mvneta_rx_queue {
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@@ -1066,20 +1070,30 @@ static void mvneta_defaults_set(struct m
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/* Enable MBUS Retry bit16 */
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mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
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- /* Set CPU queue access map. CPUs are assigned to the RX
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- * queues modulo their number and all the TX queues are
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- * assigned to the CPU associated to the default RX queue.
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+ /* Set CPU queue access map. CPUs are assigned to the RX and
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+ * TX queues modulo their number. If there is only one TX
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+ * queue then it is assigned to the CPU associated to the
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+ * default RX queue.
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*/
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for_each_present_cpu(cpu) {
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int rxq_map = 0, txq_map = 0;
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- int rxq;
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+ int rxq, txq;
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for (rxq = 0; rxq < rxq_number; rxq++)
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if ((rxq % max_cpu) == cpu)
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rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
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- if (cpu == pp->rxq_def)
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- txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
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+ for (txq = 0; txq < txq_number; txq++)
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+ if ((txq % max_cpu) == cpu)
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+ txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
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+
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+ /* With only one TX queue we configure a special case
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+ * which will allow to get all the irq on a single
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+ * CPU
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+ */
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+ if (txq_number == 1)
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+ txq_map = (cpu == pp->rxq_def) ?
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+ MVNETA_CPU_TXQ_ACCESS(1) : 0;
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mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
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}
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@@ -2366,6 +2380,8 @@ static void mvneta_rxq_deinit(struct mvn
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static int mvneta_txq_init(struct mvneta_port *pp,
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struct mvneta_tx_queue *txq)
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{
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+ int cpu;
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+
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txq->size = pp->tx_ring_size;
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/* A queue must always have room for at least one skb.
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@@ -2418,6 +2434,14 @@ static int mvneta_txq_init(struct mvneta
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}
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mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
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+ /* Setup XPS mapping */
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+ if (txq_number > 1)
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+ cpu = txq->id % num_present_cpus();
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+ else
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+ cpu = pp->rxq_def % num_present_cpus();
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+ cpumask_set_cpu(cpu, &txq->affinity_mask);
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+ netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
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+
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return 0;
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}
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@@ -2840,13 +2864,23 @@ static void mvneta_percpu_elect(struct m
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if ((rxq % max_cpu) == cpu)
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rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
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- if (i == online_cpu_idx) {
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- /* Map the default receive queue and transmit
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- * queue to the elected CPU
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+ if (i == online_cpu_idx)
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+ /* Map the default receive queue queue to the
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+ * elected CPU
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*/
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rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
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- txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
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- }
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+
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+ /* We update the TX queue map only if we have one
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+ * queue. In this case we associate the TX queue to
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+ * the CPU bound to the default RX queue
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+ */
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+ if (txq_number == 1)
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+ txq_map = (i == online_cpu_idx) ?
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+ MVNETA_CPU_TXQ_ACCESS(1) : 0;
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+ else
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+ txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
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+ MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
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+
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mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
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/* Update the interrupt mask on each CPU according the
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