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a62b1544d1
Backport various QCA8K fixes patch merged upstream. Refresh any changed patches due to backports. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
112 lines
3.7 KiB
Diff
112 lines
3.7 KiB
Diff
From a9108b0712bf018dc69020864b21485b71b17dfc Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Sun, 30 Jul 2023 09:41:12 +0200
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Subject: [PATCH 3/4] net: dsa: qca8k: move qca8xxx hol fixup to separate
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function
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Move qca8xxx hol fixup to separate function to tidy things up and to
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permit using a more efficent loop in future patch.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Link: https://lore.kernel.org/r/20230730074113.21889-4-ansuelsmth@gmail.com
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 78 +++++++++++++++++---------------
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1 file changed, 42 insertions(+), 36 deletions(-)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -1773,6 +1773,46 @@ static int qca8k_connect_tag_protocol(st
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return 0;
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}
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+static void qca8k_setup_hol_fixup(struct qca8k_priv *priv, int port)
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+{
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+ u32 mask;
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+
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+ switch (port) {
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+ /* The 2 CPU port and port 5 requires some different
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+ * priority than any other ports.
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+ */
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+ case 0:
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+ case 5:
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+ case 6:
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+ mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
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+ break;
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+ default:
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+ mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
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+ }
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+ regmap_write(priv->regmap, QCA8K_REG_PORT_HOL_CTRL0(port), mask);
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+
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+ mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
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+ QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_WRED_EN;
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+ regmap_update_bits(priv->regmap, QCA8K_REG_PORT_HOL_CTRL1(port),
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+ QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
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+ QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_WRED_EN,
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+ mask);
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+}
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+
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static int
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qca8k_setup(struct dsa_switch *ds)
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{
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@@ -1908,42 +1948,8 @@ qca8k_setup(struct dsa_switch *ds)
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* missing settings to improve switch stability under load condition.
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* This problem is limited to qca8337 and other qca8k switch are not affected.
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*/
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- if (priv->switch_id == QCA8K_ID_QCA8337) {
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- switch (i) {
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- /* The 2 CPU port and port 5 requires some different
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- * priority than any other ports.
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- */
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- case 0:
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- case 5:
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- case 6:
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- mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
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- QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
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- break;
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- default:
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- mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
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- QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
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- QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
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- }
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- qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
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-
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- mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
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- QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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- QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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- QCA8K_PORT_HOL_CTRL1_WRED_EN;
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- qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
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- QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
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- QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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- QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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- QCA8K_PORT_HOL_CTRL1_WRED_EN,
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- mask);
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- }
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+ if (priv->switch_id == QCA8K_ID_QCA8337)
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+ qca8k_setup_hol_fixup(priv, i);
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}
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/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
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