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https://github.com/openwrt/openwrt.git
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cd17d8df2a
Hardware
--------
SOC: MediaTek MT7986
RAM: 1024MB DDR3
FLASH: 128MB SPI-NAND (Winbond)
WIFI: Mediatek MT7986 DBDC 802.11ax 2.4/5 GHz
ETH: Realtek RTL8221B-VB-CG 2.5 N-Base-T PHY with PoE
UART: 3V3 115200 8N1 (Pinout silkscreened / Do not connect VCC)
Installation
------------
1. Download the OpenWrt initramfs image. Copy the image to a TFTP server
2. Connect the TFTP server to the WAX220. Conect to the serial console,
interrupt the autoboot process by pressing '0' when prompted.
3. Download & Boot the OpenWrt initramfs image.
$ setenv ipaddr 192.168.2.1
$ setenv serverip 192.168.2.2
$ tftpboot openwrt.bin
$ bootm
4. Wait for OpenWrt to boot. Transfer the sysupgrade image to the device
using scp and install using sysupgrade.
$ sysupgrade -n <path-to-sysupgrade.bin>
Signed-off-by: Flole Systems <flole@flole.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
(cherry picked from commit 984786a2f7
)
289 lines
5.1 KiB
Plaintext
289 lines
5.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include "mt7986b.dtsi"
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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model = "Netgear WAX220";
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compatible = "netgear,wax220", "mediatek,mt7986b-spim-snand-rfb";
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aliases {
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serial0 = &uart0;
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led-boot = &led_power_blue;
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led-failsafe = &led_power_amber;
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led-running = &led_power_green;
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led-upgrade = &led_power_amber;
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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label = "reset";
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};
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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wlan5g_green {
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gpios = <&pio 12 GPIO_ACTIVE_LOW>;
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label = "green:wlan5g";
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};
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led_power_amber: power_amber {
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gpios = <&pio 15 GPIO_ACTIVE_LOW>;
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label = "amber:power";
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};
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wlan2g_green {
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gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
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label = "green:wlan2g";
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};
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led_power_blue: power_blue {
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gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
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label = "blue:power";
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};
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led_power_green: power_green {
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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label = "green:power";
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};
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wlan2g_blue {
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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label = "blue:wlan2g";
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};
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lan_green {
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gpios = <&pio 22 GPIO_ACTIVE_HIGH>;
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label = "green:lan";
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};
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lan_amber {
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gpios = <&pio 13 GPIO_ACTIVE_LOW>;
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label = "amber:lan";
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};
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wlan5g_blue {
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gpios = <&pio 2 GPIO_ACTIVE_LOW>;
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label = "blue:wlan5g";
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};
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};
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};
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&crypto {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-handle = <&phy6>;
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phy-mode = "2500base-x";
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy6: ethernet-phy@6 {
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reg = <6>;
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reset-assert-us = <100000>;
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reset-deassert-us = <100000>;
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reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&pio {
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spi_flash_pins: spi-flash-pins-33-to-38 {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <8>;
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mediatek,pull-down-adv = <0>; /* bias-disable */
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};
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};
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wf_2g_5g_pins: wf_2g_5g-pins {
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mux {
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function = "wifi";
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groups = "wf_2g", "wf_5g";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <4>;
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};
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};
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wf_dbdc_pins: wf-dbdc-pins {
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mux {
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function = "wifi";
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groups = "wf_dbdc";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA";
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drive-strength = <4>;
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_flash_pins>;
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status = "okay";
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spi_nand_flash: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <20000000>;
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spi-tx-buswidth = <4>;
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spi-rx-buswidth = <4>;
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partitions: partitions {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "fixed-partitions";
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partition@5fc0000 {
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label = "Traffic";
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reg = <0x5fc0000 0x200000>;
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};
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partition@63c0000 {
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label = "NTGRcryptD";
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reg = <0x63c0000 0x500000>;
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};
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partition@580000 {
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label = "ubi";
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reg = <0x580000 0x5140000>;
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};
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factory: partition@180000 {
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label = "Factory";
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reg = <0x180000 0x200000>;
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};
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partition@69c0000 {
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label = "User_data";
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reg = <0x69c0000 0x640000>;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x100000 0x80000>;
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};
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partition@68c0000 {
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label = "LOG";
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reg = <0x68c0000 0x100000>;
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};
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partition@5ac0000 {
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label = "POT";
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reg = <0x5ac0000 0x100000>;
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};
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partition@0 {
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label = "BL2";
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read-only;
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reg = <0x0 0x100000>;
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};
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partition@5bc0000 {
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label = "Language";
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reg = <0x5bc0000 0x400000>;
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};
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partition@61c0000 {
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label = "Cert";
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reg = <0x61c0000 0x100000>;
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};
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partition@380000 {
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label = "FIP";
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reg = <0x380000 0x200000>;
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};
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partition@56c0000 {
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label = "RAE";
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reg = <0x56c0000 0x400000>;
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};
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partition@62c0000 {
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label = "NTGRcryptK";
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reg = <0x62c0000 0x100000>;
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};
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};
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};
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};
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&trng {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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status = "okay";
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pinctrl-names = "default", "dbdc";
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pinctrl-0 = <&wf_2g_5g_pins>;
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pinctrl-1 = <&wf_dbdc_pins>;
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mediatek,mtd-eeprom = <&factory 0x0>;
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};
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