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6a2e17d5c1
The driver for MediaTek gen3 PCIe hosts de-asserts all reset signals at the same time using a single register write operation. Delay the de-assertion of the #PERST signal by 100ms as some PCIe devices fail to come up otherwise. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
20 lines
677 B
Diff
20 lines
677 B
Diff
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
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+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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@@ -350,9 +350,15 @@ static int mtk_pcie_startup_port(struct
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msleep(100);
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/* De-assert reset signals */
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- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
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+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
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writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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+ msleep(100);
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+
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+ /* De-assert PERST# signals */
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+ val &= ~(PCIE_PE_RSTB);
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+ writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
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+
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/* Check if the link is up or not */
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err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
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!!(val & PCIE_PORT_LINKUP), 20,
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