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5b089e45a6
Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
56 lines
1.7 KiB
Diff
56 lines
1.7 KiB
Diff
From ab4de687cdad0adbc555237364e5a8e2cdef5144 Mon Sep 17 00:00:00 2001
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From: Remi Pommarel <repk@triplefau.lt>
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Date: Sun, 6 Dec 2015 17:22:48 +0100
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Subject: [PATCH] clk: bcm2835: Add PWM clock support
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Register the pwm clock for bcm2835.
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Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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(cherry picked from commit cfbab8fbab9c330aca963095a439c451ac97c0dd)
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---
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drivers/clk/bcm/clk-bcm2835.c | 13 +++++++++++++
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include/dt-bindings/clock/bcm2835.h | 3 ++-
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2 files changed, 15 insertions(+), 1 deletion(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -807,6 +807,16 @@ static const struct bcm2835_clock_data b
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.frac_bits = 8,
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};
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+static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
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+ .name = "pwm",
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+ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
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+ .parents = bcm2835_clock_per_parents,
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+ .ctl_reg = CM_PWMCTL,
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+ .div_reg = CM_PWMDIV,
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+ .int_bits = 12,
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+ .frac_bits = 12,
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+};
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+
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struct bcm2835_pll {
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struct clk_hw hw;
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struct bcm2835_cprman *cprman;
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@@ -1603,6 +1613,9 @@ static int bcm2835_clk_probe(struct plat
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cprman->regs + CM_PERIICTL, CM_GATE_BIT,
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0, &cprman->regs_lock);
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+ clks[BCM2835_CLOCK_PWM] =
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+ bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
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+
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return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
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&cprman->onecell);
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}
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--- a/include/dt-bindings/clock/bcm2835.h
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+++ b/include/dt-bindings/clock/bcm2835.h
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@@ -43,5 +43,6 @@
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#define BCM2835_CLOCK_TSENS 27
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#define BCM2835_CLOCK_EMMC 28
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#define BCM2835_CLOCK_PERI_IMAGE 29
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+#define BCM2835_CLOCK_PWM 30
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-#define BCM2835_CLOCK_COUNT 30
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+#define BCM2835_CLOCK_COUNT 31
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