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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
53 lines
1.6 KiB
Diff
53 lines
1.6 KiB
Diff
From f91d0e8bd6c1f812bc2589050c05a90ee886c749 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 15 May 2022 23:00:42 +0200
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Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock
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The built-in PPE engine has a dedicated clock for the EIP-197 crypto
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engine.
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So, since the required clock currently missing add support for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
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---
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drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref
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},
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};
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+static struct clk_branch gcc_crypto_ppe_clk = {
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+ .halt_reg = 0x68310,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x68310,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_crypto_ppe_clk",
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+ .parent_names = (const char *[]){
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+ "nss_ppe_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_branch gcc_nssnoc_ce_apb_clk = {
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.halt_reg = 0x6830c,
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.clkr = {
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@@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl
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[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
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[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
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[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
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+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq8074_resets[] = {
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