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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
160 lines
4.5 KiB
Diff
160 lines
4.5 KiB
Diff
From 335c32d2653f2415e042c8ad1ae2a6b33019b96f Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 12 Jun 2021 16:48:31 -0700
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Subject: [PATCH 1019/1024] soc: sifive: ccache: Add non-coherent DMA handling
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Add functions to flush the caches and handle non-coherent DMA.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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drivers/soc/sifive/sifive_ccache.c | 60 +++++++++++++++++++++++++++++-
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include/soc/sifive/sifive_ccache.h | 21 +++++++++++
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2 files changed, 80 insertions(+), 1 deletion(-)
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--- a/drivers/soc/sifive/sifive_ccache.c
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+++ b/drivers/soc/sifive/sifive_ccache.c
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@@ -8,13 +8,16 @@
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#define pr_fmt(fmt) "CCACHE: " fmt
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+#include <linux/align.h>
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#include <linux/debugfs.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/device.h>
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#include <linux/bitfield.h>
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+#include <asm/cacheflush.h>
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#include <asm/cacheinfo.h>
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+#include <asm/page.h>
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#include <soc/sifive/sifive_ccache.h>
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#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
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@@ -39,10 +42,14 @@
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#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
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#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
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+#define SIFIVE_CCACHE_FLUSH64 0x200
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+#define SIFIVE_CCACHE_FLUSH32 0x240
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+
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#define SIFIVE_CCACHE_WAYENABLE 0x08
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#define SIFIVE_CCACHE_ECCINJECTERR 0x40
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#define SIFIVE_CCACHE_MAX_ECCINTR 4
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+#define SIFIVE_CCACHE_LINE_SIZE 64
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static void __iomem *ccache_base;
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static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
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@@ -126,6 +133,47 @@ int unregister_sifive_ccache_error_notif
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}
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EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
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+#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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+static phys_addr_t uncached_offset;
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+DEFINE_STATIC_KEY_FALSE(sifive_ccache_handle_noncoherent_key);
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+
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+void sifive_ccache_flush_range(phys_addr_t start, size_t len)
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+{
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+ phys_addr_t end = start + len;
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+ phys_addr_t line;
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+
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+ if (!len)
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+ return;
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+
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+ mb();
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+ for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
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+ line += SIFIVE_CCACHE_LINE_SIZE) {
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+#ifdef CONFIG_32BIT
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+ writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
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+#else
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+ writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
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+#endif
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+ mb();
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+ }
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+}
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+EXPORT_SYMBOL_GPL(sifive_ccache_flush_range);
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+
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+void *sifive_ccache_set_uncached(void *addr, size_t size)
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+{
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+ phys_addr_t phys_addr = __pa(addr) + uncached_offset;
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+ void *mem_base;
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+
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+ mem_base = memremap(phys_addr, size, MEMREMAP_WT);
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+ if (!mem_base) {
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+ pr_err("%s memremap failed for addr %p\n", __func__, addr);
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+ return ERR_PTR(-EINVAL);
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+ }
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+
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+ return mem_base;
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+}
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+EXPORT_SYMBOL_GPL(sifive_ccache_set_uncached);
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+#endif /* CONFIG_RISCV_DMA_NONCOHERENT */
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+
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static int ccache_largest_wayenabled(void)
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{
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return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
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@@ -214,6 +262,7 @@ static int __init sifive_ccache_init(voi
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int i, rc, intr_num;
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const struct of_device_id *match;
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unsigned long broken_irqs;
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+ u64 __maybe_unused offset;
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np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
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if (!np)
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@@ -259,6 +308,15 @@ static int __init sifive_ccache_init(voi
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}
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of_node_put(np);
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+#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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+ if (!of_property_read_u64(np, "uncached-offset", &offset)) {
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+ uncached_offset = offset;
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+ static_branch_enable(&sifive_ccache_handle_noncoherent_key);
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+ riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
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+ riscv_noncoherent_supported();
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+ }
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+#endif
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+
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ccache_config_read();
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ccache_cache_ops.get_priv_group = ccache_get_priv_group;
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@@ -279,4 +337,4 @@ err_node_put:
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return rc;
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}
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-device_initcall(sifive_ccache_init);
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+arch_initcall(sifive_ccache_init);
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--- a/include/soc/sifive/sifive_ccache.h
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+++ b/include/soc/sifive/sifive_ccache.h
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@@ -7,10 +7,31 @@
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#ifndef __SOC_SIFIVE_CCACHE_H
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#define __SOC_SIFIVE_CCACHE_H
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+#include <linux/io.h>
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+#include <linux/jump_label.h>
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+
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extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
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extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
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#define SIFIVE_CCACHE_ERR_TYPE_CE 0
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#define SIFIVE_CCACHE_ERR_TYPE_UE 1
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+DECLARE_STATIC_KEY_FALSE(sifive_ccache_handle_noncoherent_key);
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+
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+static inline bool sifive_ccache_handle_noncoherent(void)
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+{
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+#ifdef CONFIG_SIFIVE_CCACHE
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+ return static_branch_unlikely(&sifive_ccache_handle_noncoherent_key);
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+#else
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+ return false;
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+#endif
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+}
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+
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+void sifive_ccache_flush_range(phys_addr_t start, size_t len);
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+void *sifive_ccache_set_uncached(void *addr, size_t size);
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+static inline void sifive_ccache_clear_uncached(void *addr, size_t size)
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+{
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+ memunmap(addr);
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+}
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+
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#endif /* __SOC_SIFIVE_CCACHE_H */
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