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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
80 lines
2.5 KiB
Diff
80 lines
2.5 KiB
Diff
From a3749d68d81488ae07878393485278eab24a5818 Mon Sep 17 00:00:00 2001
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From: William Qiu <william.qiu@starfivetech.com>
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Date: Thu, 2 Mar 2023 18:52:21 +0800
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Subject: [PATCH 095/122] spi: cadence-quadspi: Add support for StarFive JH7110
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QSPI
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Add QSPI reset operation in device probe and add RISCV support to
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QUAD SPI Kconfig.
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Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
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Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
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Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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---
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drivers/spi/Kconfig | 2 +-
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drivers/spi/spi-cadence-quadspi.c | 21 ++++++++++++++++++++-
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2 files changed, 21 insertions(+), 2 deletions(-)
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -230,7 +230,7 @@ config SPI_CADENCE
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config SPI_CADENCE_QUADSPI
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tristate "Cadence Quad SPI controller"
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- depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
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+ depends on OF && (ARM || ARM64 || X86 || RISCV || COMPILE_TEST)
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help
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Enable support for the Cadence Quad SPI Flash controller.
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--- a/drivers/spi/spi-cadence-quadspi.c
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+++ b/drivers/spi/spi-cadence-quadspi.c
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@@ -1575,7 +1575,7 @@ static int cqspi_setup_flash(struct cqsp
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static int cqspi_probe(struct platform_device *pdev)
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{
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const struct cqspi_driver_platdata *ddata;
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- struct reset_control *rstc, *rstc_ocp;
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+ struct reset_control *rstc, *rstc_ocp, *rstc_ref;
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struct device *dev = &pdev->dev;
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struct spi_master *master;
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struct resource *res_ahb;
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@@ -1668,6 +1668,17 @@ static int cqspi_probe(struct platform_d
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goto probe_reset_failed;
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}
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+ if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
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+ rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
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+ if (IS_ERR(rstc_ref)) {
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+ ret = PTR_ERR(rstc_ref);
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+ dev_err(dev, "Cannot get QSPI REF reset.\n");
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+ goto probe_reset_failed;
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+ }
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+ reset_control_assert(rstc_ref);
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+ reset_control_deassert(rstc_ref);
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+ }
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+
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reset_control_assert(rstc);
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reset_control_deassert(rstc);
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@@ -1827,6 +1838,10 @@ static const struct cqspi_driver_platdat
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.get_dma_status = cqspi_get_versal_dma_status,
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};
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+static const struct cqspi_driver_platdata jh7110_qspi = {
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+ .quirks = CQSPI_DISABLE_DAC_MODE,
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+};
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+
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static const struct of_device_id cqspi_dt_ids[] = {
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{
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.compatible = "cdns,qspi-nor",
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@@ -1852,6 +1867,10 @@ static const struct of_device_id cqspi_d
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.compatible = "intel,socfpga-qspi",
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.data = &socfpga_qspi,
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},
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+ {
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+ .compatible = "starfive,jh7110-qspi",
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+ .data = &jh7110_qspi,
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+ },
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{ /* end of table */ }
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};
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