mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
120 lines
3.3 KiB
Diff
120 lines
3.3 KiB
Diff
From 3124d653318c50e20eadbb3998eafa5928ac9b63 Mon Sep 17 00:00:00 2001
|
|
From: Changhuang Liang <changhuang.liang@starfivetech.com>
|
|
Date: Thu, 18 May 2023 23:02:02 -0700
|
|
Subject: [PATCH 073/122] soc: starfive: Add JH7110 AON PMU support
|
|
|
|
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the
|
|
dphy rx/tx power switch.
|
|
|
|
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
|
|
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
|
|
---
|
|
drivers/soc/starfive/jh71xx_pmu.c | 57 ++++++++++++++++++++++++++++---
|
|
1 file changed, 52 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/soc/starfive/jh71xx_pmu.c
|
|
+++ b/drivers/soc/starfive/jh71xx_pmu.c
|
|
@@ -2,7 +2,7 @@
|
|
/*
|
|
* StarFive JH71XX PMU (Power Management Unit) Controller Driver
|
|
*
|
|
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
|
|
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
|
|
*/
|
|
|
|
#include <linux/interrupt.h>
|
|
@@ -24,6 +24,9 @@
|
|
#define JH71XX_PMU_EVENT_STATUS 0x88
|
|
#define JH71XX_PMU_INT_STATUS 0x8C
|
|
|
|
+/* aon pmu register offset */
|
|
+#define JH71XX_AON_PMU_SWITCH 0x00
|
|
+
|
|
/* sw encourage cfg */
|
|
#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
|
|
#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
|
|
@@ -160,6 +163,26 @@ static int jh7110_pmu_set_state(struct j
|
|
return 0;
|
|
}
|
|
|
|
+static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
|
|
+{
|
|
+ struct jh71xx_pmu *pmu = pmd->pmu;
|
|
+ unsigned long flags;
|
|
+ u32 val;
|
|
+
|
|
+ spin_lock_irqsave(&pmu->lock, flags);
|
|
+ val = readl(pmu->base + JH71XX_AON_PMU_SWITCH);
|
|
+
|
|
+ if (on)
|
|
+ val |= mask;
|
|
+ else
|
|
+ val &= ~mask;
|
|
+
|
|
+ writel(val, pmu->base + JH71XX_AON_PMU_SWITCH);
|
|
+ spin_unlock_irqrestore(&pmu->lock, flags);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
|
|
{
|
|
struct jh71xx_pmu *pmu = pmd->pmu;
|
|
@@ -317,10 +340,12 @@ static int jh71xx_pmu_probe(struct platf
|
|
if (!match_data)
|
|
return -EINVAL;
|
|
|
|
- ret = match_data->pmu_parse_irq(pdev, pmu);
|
|
- if (ret) {
|
|
- dev_err(dev, "failed to parse irq\n");
|
|
- return ret;
|
|
+ if (match_data->pmu_parse_irq) {
|
|
+ ret = match_data->pmu_parse_irq(pdev, pmu);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "failed to parse irq\n");
|
|
+ return ret;
|
|
+ }
|
|
}
|
|
|
|
pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
|
|
@@ -394,11 +419,32 @@ static const struct jh71xx_pmu_match_dat
|
|
.pmu_set_state = jh7110_pmu_set_state,
|
|
};
|
|
|
|
+static const struct jh71xx_domain_info jh7110_aon_power_domains[] = {
|
|
+ [JH7110_PD_DPHY_TX] = {
|
|
+ .name = "DPHY-TX",
|
|
+ .bit = 30,
|
|
+ },
|
|
+ [JH7110_PD_DPHY_RX] = {
|
|
+ .name = "DPHY-RX",
|
|
+ .bit = 31,
|
|
+ },
|
|
+};
|
|
+
|
|
+static const struct jh71xx_pmu_match_data jh7110_aon_pmu = {
|
|
+ .num_domains = ARRAY_SIZE(jh7110_aon_power_domains),
|
|
+ .domain_info = jh7110_aon_power_domains,
|
|
+ .pmu_status = JH71XX_AON_PMU_SWITCH,
|
|
+ .pmu_set_state = jh7110_aon_pmu_set_state,
|
|
+};
|
|
+
|
|
static const struct of_device_id jh71xx_pmu_of_match[] = {
|
|
{
|
|
.compatible = "starfive,jh7110-pmu",
|
|
.data = (void *)&jh7110_pmu,
|
|
}, {
|
|
+ .compatible = "starfive,jh7110-aon-syscon",
|
|
+ .data = (void *)&jh7110_aon_pmu,
|
|
+ }, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
@@ -414,5 +460,6 @@ static struct platform_driver jh71xx_pmu
|
|
builtin_platform_driver(jh71xx_pmu_driver);
|
|
|
|
MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
|
|
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
|
|
MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
|
|
MODULE_LICENSE("GPL");
|