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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
72 lines
1.8 KiB
Diff
72 lines
1.8 KiB
Diff
From 99f0bf43994dada29e33fd8718fd25484634da3a Mon Sep 17 00:00:00 2001
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From: William Qiu <william.qiu@starfivetech.com>
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Date: Tue, 21 Mar 2023 13:52:27 +0800
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Subject: [PATCH 062/122] dt-bindings: PWM: Add StarFive PWM module
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Add documentation to describe StarFive Pulse Width Modulation
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controller driver.
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Signed-off-by: William Qiu <william.qiu@starfivetech.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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---
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.../bindings/pwm/starfive,jh7110-pwm.yaml | 53 +++++++++++++++++++
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1 file changed, 53 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
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@@ -0,0 +1,53 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pwm/starfive,jh7110-pwm.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive PWM controller
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+
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+maintainers:
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+ - William Qiu <william.qiu@starfivetech.com>
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+
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+description:
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+ StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates
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+ binary signal with user-programmable low and high periods. Clock source for the
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+ PWM can be either system clockor external clock. Each PWM timer block provides 8
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+ PWM channels.
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+
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+allOf:
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+ - $ref: pwm.yaml#
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-pwm
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 1
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+
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+ resets:
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+ maxItems: 1
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+
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+ "#pwm-cells":
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+ const: 3
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - resets
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ pwm@120d0000 {
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+ compatible = "starfive,jh7110-pwm";
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+ reg = <0x120d0000 0x10000>;
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+ clocks = <&syscrg 121>;
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+ resets = <&syscrg 108>;
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+ #pwm-cells = <3>;
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+ };
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