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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
129 lines
3.3 KiB
Diff
129 lines
3.3 KiB
Diff
From 6fd84cb9cceaa711671500a92dcee5b1072ab95a Mon Sep 17 00:00:00 2001
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From: Samin Guo <samin.guo@starfivetech.com>
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Date: Tue, 1 Nov 2022 18:11:02 +0800
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Subject: [PATCH 047/122] riscv: dts: starfive: visionfive 2: Add configuration
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of gmac and phy
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v1.3B:
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v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and
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inverse configurations.
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The tx_clk of v1.3B uses an external clock and needs to be
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switched to an external clock source.
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v1.2A:
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v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay
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configurations.
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v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to
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switch rx and rx to external clock sources.
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Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
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Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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---
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.../jh7110-starfive-visionfive-2-v1.2a.dts | 13 +++++++
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.../jh7110-starfive-visionfive-2-v1.3b.dts | 27 +++++++++++++++
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.../jh7110-starfive-visionfive-2.dtsi | 34 +++++++++++++++++++
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3 files changed, 74 insertions(+)
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--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
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@@ -11,3 +11,16 @@
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model = "StarFive VisionFive 2 v1.2A";
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compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
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};
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+
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+&gmac1 {
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+ phy-mode = "rmii";
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+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
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+ <&syscrg JH7110_SYSCLK_GMAC1_RX>;
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+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
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+ <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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+};
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+
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+&phy0 {
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+ rx-internal-delay-ps = <1900>;
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+ tx-internal-delay-ps = <1350>;
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+};
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--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
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@@ -11,3 +11,30 @@
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model = "StarFive VisionFive 2 v1.3B";
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compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
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};
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+
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+&gmac0 {
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+ starfive,tx-use-rgmii-clk;
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+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
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+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
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+};
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+
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+&gmac1 {
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+ starfive,tx-use-rgmii-clk;
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+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
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+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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+};
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+
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+&phy0 {
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+ motorcomm,tx-clk-adj-enabled;
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+ motorcomm,tx-clk-100-inverted;
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+ motorcomm,tx-clk-1000-inverted;
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+ rx-internal-delay-ps = <1500>;
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+ tx-internal-delay-ps = <1500>;
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+};
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+
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+&phy1 {
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+ motorcomm,tx-clk-adj-enabled;
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+ motorcomm,tx-clk-100-inverted;
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+ rx-internal-delay-ps = <300>;
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+ tx-internal-delay-ps = <0>;
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+};
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--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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@@ -11,6 +11,8 @@
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/ {
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aliases {
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+ ethernet0 = &gmac0;
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+ ethernet1 = &gmac1;
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i2c0 = &i2c0;
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i2c2 = &i2c2;
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i2c5 = &i2c5;
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@@ -86,6 +88,38 @@
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clock-frequency = <49152000>;
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};
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+&gmac0 {
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+ phy-handle = <&phy0>;
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+ phy-mode = "rgmii-id";
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+ status = "okay";
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "snps,dwmac-mdio";
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+
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+ phy0: ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+ };
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+};
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+
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+&gmac1 {
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+ phy-handle = <&phy1>;
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+ phy-mode = "rgmii-id";
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+ status = "okay";
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "snps,dwmac-mdio";
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+
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+ phy1: ethernet-phy@1 {
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+ reg = <0>;
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+ };
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+ };
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+};
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+
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&i2c0 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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