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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
168 lines
5.9 KiB
Diff
168 lines
5.9 KiB
Diff
From 798b9b4681be53ddbf1d8db8a88ff19aaaca500f Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 1 Apr 2023 19:19:23 +0800
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Subject: [PATCH 011/122] reset: starfive: Rename "jh7100" to "jh71x0" for the
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common code
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For the common code will be shared with the StarFive JH7110 SoC.
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Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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.../reset/starfive/reset-starfive-jh7100.c | 2 +-
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.../reset/starfive/reset-starfive-jh71x0.c | 50 +++++++++----------
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.../reset/starfive/reset-starfive-jh71x0.h | 2 +-
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3 files changed, 27 insertions(+), 27 deletions(-)
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--- a/drivers/reset/starfive/reset-starfive-jh7100.c
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+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
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@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(str
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if (IS_ERR(base))
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return PTR_ERR(base);
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- return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
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+ return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
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base + JH7100_RESET_ASSERT0,
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base + JH7100_RESET_STATUS0,
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jh7100_reset_asserted,
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--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
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+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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- * Reset driver for the StarFive JH7100 SoC
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+ * Reset driver for the StarFive JH71X0 SoCs
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*
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
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@@ -15,7 +15,7 @@
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#include "reset-starfive-jh71x0.h"
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-struct jh7100_reset {
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+struct jh71x0_reset {
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struct reset_controller_dev rcdev;
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/* protect registers against concurrent read-modify-write */
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spinlock_t lock;
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@@ -24,16 +24,16 @@ struct jh7100_reset {
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const u64 *asserted;
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};
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-static inline struct jh7100_reset *
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-jh7100_reset_from(struct reset_controller_dev *rcdev)
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+static inline struct jh71x0_reset *
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+jh71x0_reset_from(struct reset_controller_dev *rcdev)
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{
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- return container_of(rcdev, struct jh7100_reset, rcdev);
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+ return container_of(rcdev, struct jh71x0_reset, rcdev);
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}
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-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
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+static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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- struct jh7100_reset *data = jh7100_reset_from(rcdev);
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+ struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
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unsigned long offset = BIT_ULL_WORD(id);
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u64 mask = BIT_ULL_MASK(id);
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void __iomem *reg_assert = data->assert + offset * sizeof(u64);
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@@ -62,34 +62,34 @@ static int jh7100_reset_update(struct re
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return ret;
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}
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-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
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+static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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- return jh7100_reset_update(rcdev, id, true);
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+ return jh71x0_reset_update(rcdev, id, true);
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}
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-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
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+static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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- return jh7100_reset_update(rcdev, id, false);
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+ return jh71x0_reset_update(rcdev, id, false);
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}
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-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
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+static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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- ret = jh7100_reset_assert(rcdev, id);
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+ ret = jh71x0_reset_assert(rcdev, id);
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if (ret)
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return ret;
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- return jh7100_reset_deassert(rcdev, id);
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+ return jh71x0_reset_deassert(rcdev, id);
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}
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-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
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+static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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- struct jh7100_reset *data = jh7100_reset_from(rcdev);
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+ struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
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unsigned long offset = BIT_ULL_WORD(id);
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u64 mask = BIT_ULL_MASK(id);
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void __iomem *reg_status = data->status + offset * sizeof(u64);
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@@ -98,25 +98,25 @@ static int jh7100_reset_status(struct re
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return !((value ^ data->asserted[offset]) & mask);
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}
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-static const struct reset_control_ops jh7100_reset_ops = {
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- .assert = jh7100_reset_assert,
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- .deassert = jh7100_reset_deassert,
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- .reset = jh7100_reset_reset,
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- .status = jh7100_reset_status,
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+static const struct reset_control_ops jh71x0_reset_ops = {
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+ .assert = jh71x0_reset_assert,
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+ .deassert = jh71x0_reset_deassert,
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+ .reset = jh71x0_reset_reset,
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+ .status = jh71x0_reset_status,
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};
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-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
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+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
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void __iomem *assert, void __iomem *status,
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const u64 *asserted, unsigned int nr_resets,
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struct module *owner)
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{
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- struct jh7100_reset *data;
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+ struct jh71x0_reset *data;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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- data->rcdev.ops = &jh7100_reset_ops;
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+ data->rcdev.ops = &jh71x0_reset_ops;
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data->rcdev.owner = owner;
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data->rcdev.nr_resets = nr_resets;
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data->rcdev.dev = dev;
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@@ -129,4 +129,4 @@ int reset_starfive_jh7100_register(struc
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return devm_reset_controller_register(dev, &data->rcdev);
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}
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-EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
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+EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
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--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
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+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
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@@ -6,7 +6,7 @@
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#ifndef __RESET_STARFIVE_JH71X0_H
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#define __RESET_STARFIVE_JH71X0_H
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-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
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+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
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void __iomem *assert, void __iomem *status,
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const u64 *asserted, unsigned int nr_resets,
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struct module *owner);
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