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99c81eab78
Without this patch PowerCloud CR5000 AR9382 PCIe 5GHz Wifi uses the mac address from eeprom instead the one specified when initializing the PCIe chip. There were two issues: 1) ap94_pci_init on the second PCIe wmac is wrong as there is only one PCIe wmac on this device (the other wmac is the AR1022/AR9342 SoC wmac). 2) Without specifying pdata->use_eeprom there is a failure to load firmware and caldata. Thanks to Christian Lamparter (@chunkeey) for the heavy lifting and help. [0] [0] <https://github.com/openwrt/openwrt/pull/1613> Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
180 lines
5.1 KiB
C
180 lines
5.1 KiB
C
/*
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* PowerCloud Systems CR5000 support
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*
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* Copyright (c) 2011 Qualcomm Atheros
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* Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2012-2013 PowerCloud Systems
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* Copyright (c) 2015 Daniel Dickinson <openwrt@daniel.thecshore.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/gpio.h>
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define CR5000_GPIO_LED_WLAN_2G 14
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#define CR5000_GPIO_LED_WPS 12
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#define CR5000_GPIO_LED_POWER_AMBER 4
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/* GPIO2 has to have JTAG disabled as it is also to
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* power led
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*/
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#define CR5000_GPIO_LED_POWER_ENABLE 2
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#define CR5000_GPIO_BTN_WPS 16
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#define CR5000_GPIO_BTN_RESET 17
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#define CR5000_KEYS_POLL_INTERVAL 20 /* msecs */
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#define CR5000_KEYS_DEBOUNCE_INTERVAL (3 * CR5000_KEYS_POLL_INTERVAL)
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#define CR5000_MAC0_OFFSET 0
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#define CR5000_WMAC_CALDATA_OFFSET 0x1000
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#define CR5000_WMAC_MAC_OFFSET 0x1002
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#define CR5000_PCIE_CALDATA_OFFSET 0x5000
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#define CR5000_PCIE_WMAC_OFFSET 0x5002
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static struct gpio_led cr5000_leds_gpio[] __initdata = {
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{
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.name = "pcs:amber:power",
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.gpio = CR5000_GPIO_LED_POWER_AMBER,
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.active_low = 1,
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},
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{
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.name = "pcs:white:wps",
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.gpio = CR5000_GPIO_LED_WPS,
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.active_low = 1,
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},
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{
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.name = "pcs:blue:wlan",
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.gpio = CR5000_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button cr5000_gpio_keys[] __initdata = {
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{
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.desc = "WPS button",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = CR5000_KEYS_DEBOUNCE_INTERVAL,
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.gpio = CR5000_GPIO_BTN_WPS,
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.active_low = 1,
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},
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{
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.desc = "Reset button",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = CR5000_KEYS_DEBOUNCE_INTERVAL,
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.gpio = CR5000_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static struct ar8327_pad_cfg cr5000_ar8327_pad0_cfg = {
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.mode = AR8327_PAD_MAC_RGMII,
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.txclk_delay_en = true,
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.rxclk_delay_en = true,
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.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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static struct ar8327_led_cfg cr5000_ar8327_led_cfg = {
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.led_ctrl0 = 0xcc35cc35,
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.led_ctrl1 = 0xca35ca35,
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.led_ctrl2 = 0xc935c935,
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.led_ctrl3 = 0x03ffff00,
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.open_drain = true,
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};
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static struct ar8327_platform_data cr5000_ar8327_data = {
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.pad0_cfg = &cr5000_ar8327_pad0_cfg,
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.port0_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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},
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.led_cfg = &cr5000_ar8327_led_cfg,
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};
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static struct mdio_board_info cr5000_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.mdio_addr = 0,
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.platform_data = &cr5000_ar8327_data,
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},
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};
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static void __init cr5000_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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struct ath9k_platform_data *pdata;
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ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
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gpio_request_one(CR5000_GPIO_LED_POWER_ENABLE,
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GPIOF_OUT_INIT_LOW, "Power LED enable");
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ath79_gpio_output_select(CR5000_GPIO_LED_POWER_AMBER, AR934X_GPIO_OUT_GPIO);
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ath79_gpio_output_select(CR5000_GPIO_LED_WLAN_2G, AR934X_GPIO_OUT_GPIO);
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ath79_gpio_output_select(CR5000_GPIO_LED_WPS, AR934X_GPIO_OUT_GPIO);
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(cr5000_leds_gpio),
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cr5000_leds_gpio);
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ath79_register_gpio_keys_polled(-1, CR5000_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(cr5000_gpio_keys),
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cr5000_gpio_keys);
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ath79_register_usb();
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ath79_register_wmac(art + CR5000_WMAC_CALDATA_OFFSET, art + CR5000_WMAC_MAC_OFFSET);
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ap91_pci_init(NULL, art + CR5000_PCIE_WMAC_OFFSET);
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pdata = ap9x_pci_get_wmac_data(0);
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if (pdata)
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pdata->use_eeprom = true;
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
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ath79_register_mdio(0, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, art + CR5000_MAC0_OFFSET, 0);
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mdiobus_register_board_info(cr5000_mdio0_info,
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ARRAY_SIZE(cr5000_mdio0_info));
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/* GMAC0 is connected to an AR8327 switch */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_pll_data.pll_1000 = 0x06000000;
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ath79_register_eth(0);
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}
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MIPS_MACHINE(ATH79_MACH_CR5000, "CR5000", "PowerCloud Systems CR5000",
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cr5000_setup);
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