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7e20e4ab96
Refreshed all patches. Removed upstreamed hunks in: - 703-phy-support-layerscape.patch Compile-tested on: ar71xx, layerscape Runtime-tested on: ar71xx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
236 lines
6.4 KiB
Diff
236 lines
6.4 KiB
Diff
From 21ff843931b2e5a9b628ac56fd0f2e4355890096 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Mon, 19 Sep 2016 10:43:18 +0200
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Subject: [PATCH] ARM: dts: bcm283x: Define standard pinctrl groups in the gpio
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node.
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The BCM2835-ARM-Peripherals.pdf documentation specifies what the
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function selects do for the pins, and there are a bunch of obvious
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groupings to be made. With these created, we'll be able to replace
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bcm2835-rpi.dtsi's main "set all of these pins to alt0" with
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references to specific groups we want enabled.
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Also add pinctrl groups for emmc and sdhost.
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Based on patches by Eric Anholt, with fixups by Gerd Hoffmann.
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
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---
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arch/arm/boot/dts/bcm283x.dtsi | 203 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 203 insertions(+)
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--- a/arch/arm/boot/dts/bcm283x.dtsi
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+++ b/arch/arm/boot/dts/bcm283x.dtsi
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@@ -137,6 +137,209 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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+
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+ /* Defines pin muxing groups according to
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+ * BCM2835-ARM-Peripherals.pdf page 102.
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+ *
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+ * While each pin can have its mux selected
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+ * for various functions individually, some
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+ * groups only make sense to switch to a
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+ * particular function together.
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+ */
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+ dpi_gpio0: dpi_gpio0 {
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+ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
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+ 12 13 14 15 16 17 18 19
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+ 20 21 22 23 24 25 26 27>;
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+ brcm,function = <BCM2835_FSEL_ALT2>;
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+ };
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+ emmc_gpio22: emmc_gpio22 {
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+ brcm,pins = <22 23 24 25 26 27>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+ emmc_gpio34: emmc_gpio34 {
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+ brcm,pins = <34 35 36 37 38 39>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ brcm,pull = <BCM2835_PUD_OFF
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+ BCM2835_PUD_UP
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+ BCM2835_PUD_UP
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+ BCM2835_PUD_UP
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+ BCM2835_PUD_UP
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+ BCM2835_PUD_UP>;
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+ };
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+ emmc_gpio48: emmc_gpio48 {
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+ brcm,pins = <48 49 50 51 52 53>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+
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+ gpclk0_gpio4: gpclk0_gpio4 {
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+ brcm,pins = <4>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ gpclk1_gpio5: gpclk1_gpio5 {
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+ brcm,pins = <5>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ gpclk1_gpio42: gpclk1_gpio42 {
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+ brcm,pins = <42>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ gpclk1_gpio44: gpclk1_gpio44 {
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+ brcm,pins = <44>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ gpclk2_gpio6: gpclk2_gpio6 {
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+ brcm,pins = <6>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ gpclk2_gpio43: gpclk2_gpio43 {
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+ brcm,pins = <43>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+
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+ i2c0_gpio0: i2c0_gpio0 {
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+ brcm,pins = <0 1>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ i2c0_gpio32: i2c0_gpio32 {
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+ brcm,pins = <32 34>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ i2c0_gpio44: i2c0_gpio44 {
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+ brcm,pins = <44 45>;
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+ brcm,function = <BCM2835_FSEL_ALT1>;
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+ };
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+ i2c1_gpio2: i2c1_gpio2 {
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+ brcm,pins = <2 3>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ i2c1_gpio44: i2c1_gpio44 {
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+ brcm,pins = <44 45>;
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+ brcm,function = <BCM2835_FSEL_ALT2>;
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+ };
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+ i2c_slave_gpio18: i2c_slave_gpio18 {
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+ brcm,pins = <18 19 20 21>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+
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+ jtag_gpio4: jtag_gpio4 {
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+ brcm,pins = <4 5 6 12 13>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ };
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+ jtag_gpio22: jtag_gpio22 {
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+ brcm,pins = <22 23 24 25 26 27>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ };
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+
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+ pcm_gpio18: pcm_gpio18 {
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+ brcm,pins = <18 19 20 21>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ pcm_gpio28: pcm_gpio28 {
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+ brcm,pins = <28 29 30 31>;
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+ brcm,function = <BCM2835_FSEL_ALT2>;
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+ };
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+
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+ pwm0_gpio12: pwm0_gpio12 {
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+ brcm,pins = <12>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ pwm0_gpio18: pwm0_gpio18 {
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+ brcm,pins = <18>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+ pwm0_gpio40: pwm0_gpio40 {
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+ brcm,pins = <40>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ pwm1_gpio13: pwm1_gpio13 {
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+ brcm,pins = <13>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ pwm1_gpio19: pwm1_gpio19 {
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+ brcm,pins = <19>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+ pwm1_gpio41: pwm1_gpio41 {
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+ brcm,pins = <41>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ pwm1_gpio45: pwm1_gpio45 {
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+ brcm,pins = <45>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+
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+ sdhost_gpio48: sdhost_gpio48 {
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+ brcm,pins = <48 49 50 51 52 53>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+
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+ spi0_gpio7: spi0_gpio7 {
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+ brcm,pins = <7 8 9 10 11>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ spi0_gpio35: spi0_gpio35 {
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+ brcm,pins = <35 36 37 38 39>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ spi1_gpio16: spi1_gpio16 {
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+ brcm,pins = <16 17 18 19 20 21>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ };
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+ spi2_gpio40: spi2_gpio40 {
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+ brcm,pins = <40 41 42 43 44 45>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ };
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+
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+ uart0_gpio14: uart0_gpio14 {
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+ brcm,pins = <14 15>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+ /* Separate from the uart0_gpio14 group
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+ * because it conflicts with spi1_gpio16, and
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+ * people often run uart0 on the two pins
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+ * without flow contrl.
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+ */
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+ uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
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+ brcm,pins = <16 17>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+ uart0_gpio30: uart0_gpio30 {
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+ brcm,pins = <30 31>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+ uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
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+ brcm,pins = <32 33>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+
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+ uart1_gpio14: uart1_gpio14 {
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+ brcm,pins = <14 15>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+ uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
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+ brcm,pins = <16 17>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+ uart1_gpio32: uart1_gpio32 {
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+ brcm,pins = <32 33>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
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+ brcm,pins = <30 31>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+ uart1_gpio36: uart1_gpio36 {
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+ brcm,pins = <36 37 38 39>;
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+ brcm,function = <BCM2835_FSEL_ALT2>;
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+ };
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+ uart1_gpio40: uart1_gpio40 {
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+ brcm,pins = <40 41>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+ uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
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+ brcm,pins = <42 43>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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};
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uart0: serial@7e201000 {
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