mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
e8096de9a2
Remove whitespace from otherwise empty lines Signed-off-by: Felix Baumann <felix.bau@gmx.de>
321 lines
6.3 KiB
Plaintext
321 lines
6.3 KiB
Plaintext
/dts-v1/;
|
|
|
|
#include "rtl839x.dtsi"
|
|
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc";
|
|
model = "Zyxel GS1900-48";
|
|
|
|
aliases {
|
|
led-boot = &led_sys;
|
|
led-failsafe = &led_sys;
|
|
led-running = &led_sys;
|
|
led-upgrade = &led_sys;
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x8000000>;
|
|
};
|
|
|
|
leds {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinmux_disable_sys_led>;
|
|
compatible = "gpio-leds";
|
|
|
|
led_sys: sys {
|
|
label = "green:sys";
|
|
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio1: rtl8231-gpio {
|
|
compatible = "realtek,rtl8231-gpio";
|
|
#gpio-cells = <2>;
|
|
indirect-access-bus-id = <3>;
|
|
gpio-controller;
|
|
};
|
|
|
|
gpio-restart {
|
|
compatible = "gpio-restart";
|
|
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys-polled";
|
|
poll-interval = <20>;
|
|
|
|
mode {
|
|
label = "reset";
|
|
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
|
|
/* i2c of the left SFP cage: port 49 */
|
|
i2c0: i2c-gpio-0 {
|
|
compatible = "i2c-gpio";
|
|
sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
i2c-gpio,delay-us = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
sfp0: sfp-p9 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c0>;
|
|
los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
|
|
tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
|
|
tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
/* i2c of the right SFP cage: port 50 */
|
|
i2c1: i2c-gpio-1 {
|
|
compatible = "i2c-gpio";
|
|
sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
i2c-gpio,delay-us = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
sfp1: sfp-p10 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c1>;
|
|
los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
|
|
tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
|
|
tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <10000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x0 0x40000>;
|
|
read-only;
|
|
};
|
|
partition@40000 {
|
|
label = "u-boot-env";
|
|
reg = <0x40000 0x10000>;
|
|
read-only;
|
|
};
|
|
partition@50000 {
|
|
label = "u-boot-env2";
|
|
reg = <0x50000 0x10000>;
|
|
read-only;
|
|
};
|
|
partition@60000 {
|
|
label = "jffs";
|
|
reg = <0x60000 0x100000>;
|
|
};
|
|
partition@160000 {
|
|
label = "jffs2";
|
|
reg = <0x160000 0x100000>;
|
|
};
|
|
partition@260000 {
|
|
label = "firmware";
|
|
reg = <0x260000 0x6d0000>;
|
|
compatible = "openwrt,uimage", "denx,uimage";
|
|
openwrt,ih-magic = <0x83800000>;
|
|
};
|
|
partition@930000 {
|
|
label = "runtime2";
|
|
reg = <0x930000 0x6d0000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ðernet0 {
|
|
mdio: mdio-bus {
|
|
compatible = "realtek,rtl838x-mdio";
|
|
regmap = <ðernet0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/* External phy RTL8218B #1 */
|
|
EXTERNAL_PHY(0)
|
|
EXTERNAL_PHY(1)
|
|
EXTERNAL_PHY(2)
|
|
EXTERNAL_PHY(3)
|
|
EXTERNAL_PHY(4)
|
|
EXTERNAL_PHY(5)
|
|
EXTERNAL_PHY(6)
|
|
EXTERNAL_PHY(7)
|
|
|
|
/* External phy RTL8218B #2 */
|
|
EXTERNAL_PHY(8)
|
|
EXTERNAL_PHY(9)
|
|
EXTERNAL_PHY(10)
|
|
EXTERNAL_PHY(11)
|
|
EXTERNAL_PHY(12)
|
|
EXTERNAL_PHY(13)
|
|
EXTERNAL_PHY(14)
|
|
EXTERNAL_PHY(15)
|
|
|
|
/* External phy RTL8218B #3 */
|
|
EXTERNAL_PHY(16)
|
|
EXTERNAL_PHY(17)
|
|
EXTERNAL_PHY(18)
|
|
EXTERNAL_PHY(19)
|
|
EXTERNAL_PHY(20)
|
|
EXTERNAL_PHY(21)
|
|
EXTERNAL_PHY(22)
|
|
EXTERNAL_PHY(23)
|
|
|
|
/* External phy RTL8218B #4 */
|
|
EXTERNAL_PHY(24)
|
|
EXTERNAL_PHY(25)
|
|
EXTERNAL_PHY(26)
|
|
EXTERNAL_PHY(27)
|
|
EXTERNAL_PHY(28)
|
|
EXTERNAL_PHY(29)
|
|
EXTERNAL_PHY(30)
|
|
EXTERNAL_PHY(31)
|
|
|
|
/* External phy RTL8218B #5 */
|
|
EXTERNAL_PHY(32)
|
|
EXTERNAL_PHY(33)
|
|
EXTERNAL_PHY(34)
|
|
EXTERNAL_PHY(35)
|
|
EXTERNAL_PHY(36)
|
|
EXTERNAL_PHY(37)
|
|
EXTERNAL_PHY(38)
|
|
EXTERNAL_PHY(39)
|
|
|
|
/* External phy RTL8218B #6 */
|
|
EXTERNAL_PHY(40)
|
|
EXTERNAL_PHY(41)
|
|
EXTERNAL_PHY(42)
|
|
EXTERNAL_PHY(43)
|
|
EXTERNAL_PHY(44)
|
|
EXTERNAL_PHY(45)
|
|
EXTERNAL_PHY(46)
|
|
EXTERNAL_PHY(47)
|
|
|
|
/* RTL8393 Internal SerDes */
|
|
INTERNAL_PHY(48)
|
|
INTERNAL_PHY(49)
|
|
};
|
|
};
|
|
|
|
&switch0 {
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
SWITCH_PORT(0, 01, qsgmii)
|
|
SWITCH_PORT(1, 02, qsgmii)
|
|
SWITCH_PORT(2, 03, qsgmii)
|
|
SWITCH_PORT(3, 04, qsgmii)
|
|
SWITCH_PORT(4, 05, qsgmii)
|
|
SWITCH_PORT(5, 06, qsgmii)
|
|
SWITCH_PORT(6, 07, qsgmii)
|
|
SWITCH_PORT(7, 08, qsgmii)
|
|
|
|
SWITCH_PORT(8, 09, qsgmii)
|
|
SWITCH_PORT(9, 10, qsgmii)
|
|
SWITCH_PORT(10, 11, qsgmii)
|
|
SWITCH_PORT(11, 12, qsgmii)
|
|
SWITCH_PORT(12, 13, qsgmii)
|
|
SWITCH_PORT(13, 14, qsgmii)
|
|
SWITCH_PORT(14, 15, qsgmii)
|
|
SWITCH_PORT(15, 16, qsgmii)
|
|
|
|
SWITCH_PORT(16, 17, qsgmii)
|
|
SWITCH_PORT(17, 18, qsgmii)
|
|
SWITCH_PORT(18, 19, qsgmii)
|
|
SWITCH_PORT(19, 20, qsgmii)
|
|
SWITCH_PORT(20, 21, qsgmii)
|
|
SWITCH_PORT(21, 22, qsgmii)
|
|
SWITCH_PORT(22, 23, qsgmii)
|
|
SWITCH_PORT(23, 24, qsgmii)
|
|
|
|
SWITCH_PORT(24, 25, qsgmii)
|
|
SWITCH_PORT(25, 26, qsgmii)
|
|
SWITCH_PORT(26, 27, qsgmii)
|
|
SWITCH_PORT(27, 28, qsgmii)
|
|
SWITCH_PORT(28, 29, qsgmii)
|
|
SWITCH_PORT(29, 30, qsgmii)
|
|
SWITCH_PORT(30, 31, qsgmii)
|
|
SWITCH_PORT(31, 32, qsgmii)
|
|
|
|
SWITCH_PORT(32, 33, qsgmii)
|
|
SWITCH_PORT(33, 34, qsgmii)
|
|
SWITCH_PORT(34, 35, qsgmii)
|
|
SWITCH_PORT(35, 36, qsgmii)
|
|
SWITCH_PORT(36, 37, qsgmii)
|
|
SWITCH_PORT(37, 38, qsgmii)
|
|
SWITCH_PORT(38, 39, qsgmii)
|
|
SWITCH_PORT(39, 40, qsgmii)
|
|
|
|
SWITCH_PORT(40, 41, qsgmii)
|
|
SWITCH_PORT(41, 42, qsgmii)
|
|
SWITCH_PORT(42, 43, qsgmii)
|
|
SWITCH_PORT(43, 44, qsgmii)
|
|
SWITCH_PORT(44, 45, qsgmii)
|
|
SWITCH_PORT(45, 46, qsgmii)
|
|
SWITCH_PORT(46, 47, qsgmii)
|
|
SWITCH_PORT(47, 48, qsgmii)
|
|
|
|
/* SFP cages */
|
|
port@48 {
|
|
reg = <48>;
|
|
label = "lan49";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&phy48>;
|
|
sfp = <&sfp0>;
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
|
|
};
|
|
|
|
port@49 {
|
|
reg = <49>;
|
|
label = "lan50";
|
|
phy-mode = "sgmii";
|
|
phy-handle = <&phy49>;
|
|
sfp = <&sfp1>;
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
|
|
};
|
|
|
|
/* CPU-Port */
|
|
port@52 {
|
|
ethernet = <ðernet0>;
|
|
reg = <52>;
|
|
phy-mode = "qsgmii";
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
};
|
|
};
|