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8b66f1a06d
For all boards currently working with the mt7530 DSA driver we can be sure that the address of the switch on the MDIO bus is 31 -- simply because that address is hard-coded in the driver and the address from the Device Tree is being ignore. An upcoming patch will add support for MT753x ICs which are programmed to addresses different from 0x1f using bootstrap pins. As a result the address from the Device Tree will then be taken into account, which will break currently working boards which got the address set to anything else than 31. While at it also unify the syntax in Device Tree to always us a decimal value for the 'reg' property. * mt7622-buffalo-wsr-3200ax4s.dts Cosmetic change 'reg = <0x1f>' -> 'reg = <31>' * mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi Wrong address: 0 -> 31 * mt7622-elecom-wrc-x3200gst3.dts Wrong address: 0 -> 31 * mt7622-linksys-e8450.dtsi Wrong address: 0 -> 31 * mt7622-ruijie-rg-ew3200.dtsi Wrong address: 0 -> 31 * mt7622-xiaomi-redmi-router-ax6s.dts Wrong address: 0 -> 31 * mt7629-iptime-a6004mx.dts Wrong address: 2 -> 31 * mt7981b-zbtlink-zbt-z8102ax.dts Cosmetic change 'reg = <0x1f>' -> 'reg = <31>' Signed-off-by: Daniel Golle <daniel@makrotopia.org>
433 lines
7.2 KiB
Plaintext
433 lines
7.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include "mt7622.dtsi"
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#include "mt6380.dtsi"
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/ {
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model = "ELECOM WRC-X3200GST3";
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compatible = "elecom,wrc-x3200gst3", "mediatek,mt7622";
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aliases {
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serial0 = &uart0;
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led-boot = &led_power_green;
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led-failsafe = &led_power_red;
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led-running = &led_power_green;
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led-upgrade = &led_power_green;
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label-mac-device = &wan;
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};
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
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};
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memory {
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reg = <0 0x40000000 0 0x1f000000>;
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};
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leds {
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compatible = "gpio-leds";
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led-0 {
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gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_WPS;
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};
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led_power_red: led-1 {
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gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_POWER;
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function-enumerator = <1>;
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};
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led_power_green: led-2 {
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gpios = <&pio 49 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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function-enumerator = <2>;
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};
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led-3 {
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gpios = <&pio 50 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_POWER;
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function-enumerator = <3>;
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};
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led-4 {
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gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_WHITE>;
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function = LED_FUNCTION_WLAN;
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function-enumerator = <1>;
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linux,default-trigger = "phy0tpt";
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};
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led-5 {
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gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_WHITE>;
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function = LED_FUNCTION_WLAN;
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function-enumerator = <2>;
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linux,default-trigger = "phy1radio";
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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ap {
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label = "ap";
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gpios = <&pio 42 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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linux,input-type = <EV_SW>;
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};
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router {
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label = "router";
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gpios = <&pio 43 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_1>;
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linux,input-type = <EV_SW>;
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};
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wps {
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label = "wps";
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gpios = <&pio 102 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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};
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&cpu0 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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&cpu1 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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&pio {
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eth_pins: eth-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio", "rgmii_via_gmac2";
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};
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};
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie0_pad_perst",
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"pcie0_1_waken",
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"pcie0_1_clkreq";
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};
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};
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pmic_bus_pins: pmic-bus-pins {
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mux {
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function = "pmic";
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groups = "pmic_bus";
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};
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};
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pwm7_pins: pwm1-2-pins {
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mux {
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function = "pwm";
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groups = "pwm_ch7_2";
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};
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};
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/* Serial NAND is shared pin with SPI-NOR */
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serial_nand_pins: serial-nand-pins {
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mux {
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function = "flash";
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groups = "snfi";
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};
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conf-cmd-data {
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pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI",
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"SPI_MISO", "SPI_CS";
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drive-strength = <16>;
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bias-pull-up;
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};
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conf-clk {
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pins = "SPI_CLK";
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drive-strength = <16>;
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bias-pull-down;
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};
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};
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0_0_tx_rx" ;
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};
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};
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watchdog_pins: watchdog-pins {
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mux {
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function = "watchdog";
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groups = "watchdog";
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};
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};
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};
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ð {
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pinctrl-names = "default";
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pinctrl-0 = <ð_pins>;
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-connection-type = "2500base-x";
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nvmem-cells = <&macaddr_factory_7fff4>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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wan: port@0 {
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reg = <0>;
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label = "wan";
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nvmem-cells = <&macaddr_factory_7fffa>;
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nvmem-cell-names = "mac-address";
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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&bch {
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status = "okay";
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};
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&snfi {
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pinctrl-names = "default";
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pinctrl-0 = <&serial_nand_pins>;
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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nand-ecc-engine = <&snfi>;
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mediatek,bmt-v2;
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mediatek,bmt-table-size = <0x1000>;
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mediatek,bmt-remap-range = <0x0 0x8c0000>,
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<0x1bc0000 0x30c0000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Preloader";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "ATF";
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reg = <0x80000 0x40000>;
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read-only;
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};
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partition@c0000 {
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label = "u-boot";
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reg = <0xc0000 0x80000>;
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read-only;
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};
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partition@140000 {
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label = "u-boot-env";
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reg = <0x140000 0x80000>;
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read-only;
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};
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factory: partition@1c0000 {
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label = "factory";
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reg = <0x1c0000 0x100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_4: macaddr@4 {
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compatible = "mac-base";
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reg = <0x4 0x6>;
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#nvmem-cell-cells = <1>;
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};
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macaddr_factory_7fff4: macaddr@7fff4 {
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reg = <0x7fff4 0x6>;
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};
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macaddr_factory_7fffa: macaddr@7fffa {
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reg = <0x7fffa 0x6>;
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};
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};
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};
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partition@2c0000 {
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label = "kernel";
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reg = <0x2c0000 0x600000>;
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};
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partition@8c0000 {
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label = "ubi";
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reg = <0x8c0000 0x1300000>;
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};
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partition@1bc0000 {
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label = "tm_pattern";
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reg = <0x1bc0000 0x500000>;
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read-only;
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};
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partition@20c0000 {
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label = "tm_key";
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reg = <0x20c0000 0x100000>;
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read-only;
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};
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partition@21c0000 {
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label = "user_data";
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reg = <0x21c0000 0xf00000>;
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read-only;
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};
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partition@30c0000 {
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label = "reserved";
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reg = <0x30c0000 0x4f40000>;
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read-only;
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};
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};
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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};
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&slot0 {
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status = "okay";
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x5000>;
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ieee80211-freq-limit = <5000000 6000000>;
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nvmem-cells = <&macaddr_factory_4 1>;
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nvmem-cell-names = "mac-address";
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm7_pins>;
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status = "okay";
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};
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&pwrap {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_bus_pins>;
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status = "okay";
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};
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&rtc {
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status = "disabled";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&watchdog {
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pinctrl-names = "default";
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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&wmac {
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status = "okay";
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mediatek,mtd-eeprom = <&factory 0x0>;
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};
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