mirror of
https://github.com/openwrt/openwrt.git
synced 2025-01-02 03:56:49 +00:00
7d7aa2fd92
This change makes the names of Broadcom targets consistent by using the common notation based on SoC/CPU ID (which is used internally anyway), bcmXXXX instead of brcmXXXX. This is even used for target TITLE in make menuconfig already, only the short target name used brcm so far. Despite, since subtargets range from bcm2708 to bcm2711, it seems appropriate to use bcm27xx instead of bcm2708 (again, as already done for BOARDNAME). This also renames the packages brcm2708-userland and brcm2708-gpu-fw. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Acked-by: Álvaro Fernández Rojas <noltari@gmail.com>
89 lines
2.9 KiB
Diff
89 lines
2.9 KiB
Diff
From 4b777f389e22abb364e398f45673e54bcda9cc55 Mon Sep 17 00:00:00 2001
|
|
From: Phil Elwell <phil@raspberrypi.org>
|
|
Date: Fri, 12 Jul 2019 11:41:25 +0100
|
|
Subject: [PATCH] pcie-brcmstb: Bounce buffer support is for BCM2711B0
|
|
|
|
Add a new compatible string to identify BCM2711B0, as later revisions
|
|
don't require the bounce buffer support.
|
|
|
|
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
|
|
---
|
|
drivers/pci/controller/pcie-brcmstb.c | 31 +++++++++++++++++++++++----
|
|
1 file changed, 27 insertions(+), 4 deletions(-)
|
|
|
|
--- a/drivers/pci/controller/pcie-brcmstb.c
|
|
+++ b/drivers/pci/controller/pcie-brcmstb.c
|
|
@@ -206,6 +206,8 @@ enum pcie_type {
|
|
BCM7435,
|
|
GENERIC,
|
|
BCM7278,
|
|
+ BCM2711B0,
|
|
+ BCM2711,
|
|
};
|
|
|
|
struct brcm_window {
|
|
@@ -302,6 +304,20 @@ static const int pcie_offsets[] = {
|
|
[EXT_CFG_DATA] = 0x8000,
|
|
};
|
|
|
|
+static const struct pcie_cfg_data bcm2711b0_cfg = {
|
|
+ .reg_field_info = pcie_reg_field_info,
|
|
+ .offsets = pcie_offsets,
|
|
+ .max_burst_size = BURST_SIZE_128,
|
|
+ .type = BCM2711B0,
|
|
+};
|
|
+
|
|
+static const struct pcie_cfg_data bcm2711_cfg = {
|
|
+ .reg_field_info = pcie_reg_field_info,
|
|
+ .offsets = pcie_offsets,
|
|
+ .max_burst_size = BURST_SIZE_128,
|
|
+ .type = BCM2711,
|
|
+};
|
|
+
|
|
static const struct pcie_cfg_data bcm7435_cfg = {
|
|
.reg_field_info = pcie_reg_field_info,
|
|
.offsets = pcie_offsets,
|
|
@@ -312,7 +328,7 @@ static const struct pcie_cfg_data bcm743
|
|
static const struct pcie_cfg_data generic_cfg = {
|
|
.reg_field_info = pcie_reg_field_info,
|
|
.offsets = pcie_offsets,
|
|
- .max_burst_size = BURST_SIZE_128, // before BURST_SIZE_512
|
|
+ .max_burst_size = BURST_SIZE_512,
|
|
.type = GENERIC,
|
|
};
|
|
|
|
@@ -380,7 +396,7 @@ static unsigned int bounce_buffer = 32*1
|
|
module_param(bounce_buffer, uint, 0644);
|
|
MODULE_PARM_DESC(bounce_buffer, "Size of bounce buffer");
|
|
|
|
-static unsigned int bounce_threshold = 0xc0000000;
|
|
+static unsigned int bounce_threshold;
|
|
module_param(bounce_threshold, uint, 0644);
|
|
MODULE_PARM_DESC(bounce_threshold, "Bounce threshold");
|
|
|
|
@@ -1681,6 +1697,8 @@ static int brcm_pcie_remove(struct platf
|
|
}
|
|
|
|
static const struct of_device_id brcm_pcie_match[] = {
|
|
+ { .compatible = "brcm,bcm2711b0-pcie", .data = &bcm2711b0_cfg },
|
|
+ { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
|
|
{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
|
|
{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
|
|
{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
|
|
@@ -1736,8 +1754,13 @@ static int brcm_pcie_probe(struct platfo
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
- /* To Do: Add hardware check if this ever gets fixed */
|
|
- if (max_pfn > (bounce_threshold/PAGE_SIZE)) {
|
|
+ if (!bounce_threshold) {
|
|
+ /* PCIe on BCM2711B0 can only address 3GB */
|
|
+ if (pcie->type == BCM2711B0 || pcie->type == GENERIC)
|
|
+ bounce_threshold = 0xc0000000;
|
|
+ }
|
|
+
|
|
+ if (bounce_threshold && (max_pfn > (bounce_threshold/PAGE_SIZE))) {
|
|
int ret;
|
|
ret = brcm_pcie_bounce_init(&pdev->dev, bounce_buffer,
|
|
(dma_addr_t)bounce_threshold);
|