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b9d8c81018
This is not a strict rule but it matches better this one: 7xx - network / phy driver patches Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
253 lines
8.0 KiB
Diff
253 lines
8.0 KiB
Diff
From d3feb406733544dbf0e239ef945a09decdceac88 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Thu, 14 Apr 2016 11:37:43 +0200
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Subject: [PATCH] phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Northstar is a family of SoCs used in home routers. They have USB 2.0
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and 3.0 controllers with PHYs that need to be properly initialized.
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This driver provides PHY init support in a generic way and can be bound
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with an EHCI controller driver.
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There are (just a few) registers being defined in bcma header. It's
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because DMU/CRU registers will be also needed in other drivers. We will
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need them e.g. in PCIe controller/PHY driver and at some point probably
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in clock driver for BCM53573 chipset. By using include/linux/bcma/ we
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avoid code duplication.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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---
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.../devicetree/bindings/phy/bcm-ns-usb2-phy.txt | 21 ++++
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drivers/phy/Kconfig | 9 ++
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drivers/phy/Makefile | 1 +
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drivers/phy/phy-bcm-ns-usb2.c | 137 +++++++++++++++++++++
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include/linux/bcma/bcma.h | 1 +
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include/linux/bcma/bcma_driver_arm_c9.h | 15 +++
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6 files changed, 184 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt
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create mode 100644 drivers/phy/phy-bcm-ns-usb2.c
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create mode 100644 include/linux/bcma/bcma_driver_arm_c9.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt
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@@ -0,0 +1,21 @@
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+Driver for Broadcom Northstar USB 2.0 PHY
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+
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+Required properties:
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+- compatible: brcm,ns-usb2-phy
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+- reg: iomem address range of DMU (Device Management Unit)
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+- reg-names: "dmu", the only needed & supported reg right now
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+- clocks: USB PHY reference clock
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+- clock-names: "phy-ref-clk", the only needed & supported clock right now
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+
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+To initialize USB 2.0 PHY driver needs to setup PLL correctly. To do this it
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+requires passing phandle to the USB PHY reference clock.
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+
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+Example:
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+ usb2-phy {
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+ compatible = "brcm,ns-usb2-phy";
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+ reg = <0x1800c000 0x1000>;
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+ reg-names = "dmu";
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+ #phy-cells = <0>;
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+ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
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+ clock-names = "phy-ref-clk";
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+ };
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--- a/drivers/phy/Kconfig
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+++ b/drivers/phy/Kconfig
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@@ -15,6 +15,15 @@ config GENERIC_PHY
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phy users can obtain reference to the PHY. All the users of this
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framework should select this config.
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+config PHY_BCM_NS_USB2
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+ tristate "Broadcom Northstar USB 2.0 PHY Driver"
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+ depends on ARCH_BCM_IPROC || COMPILE_TEST
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+ depends on HAS_IOMEM && OF
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+ select GENERIC_PHY
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+ help
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+ Enable this to support Broadcom USB 2.0 PHY connected to the USB
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+ controller on Northstar family.
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+
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config PHY_BERLIN_USB
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tristate "Marvell Berlin USB PHY Driver"
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depends on ARCH_BERLIN && RESET_CONTROLLER && HAS_IOMEM && OF
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--- a/drivers/phy/Makefile
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+++ b/drivers/phy/Makefile
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@@ -3,6 +3,7 @@
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#
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obj-$(CONFIG_GENERIC_PHY) += phy-core.o
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+obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o
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obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
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obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
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obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
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--- /dev/null
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+++ b/drivers/phy/phy-bcm-ns-usb2.c
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@@ -0,0 +1,137 @@
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+/*
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+ * Broadcom Northstar USB 2.0 PHY Driver
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+ *
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+ * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#include <linux/bcma/bcma.h>
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/module.h>
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+#include <linux/of_address.h>
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+#include <linux/of_platform.h>
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+#include <linux/phy/phy.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+
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+struct bcm_ns_usb2 {
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+ struct device *dev;
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+ struct clk *ref_clk;
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+ struct phy *phy;
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+ void __iomem *dmu;
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+};
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+
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+static int bcm_ns_usb2_phy_init(struct phy *phy)
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+{
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+ struct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy);
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+ struct device *dev = usb2->dev;
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+ void __iomem *dmu = usb2->dmu;
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+ u32 ref_clk_rate, usb2ctl, usb_pll_ndiv, usb_pll_pdiv;
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+ int err = 0;
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+
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+ err = clk_prepare_enable(usb2->ref_clk);
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+ if (err < 0) {
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+ dev_err(dev, "Failed to prepare ref clock: %d\n", err);
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+ goto err_out;
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+ }
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+
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+ ref_clk_rate = clk_get_rate(usb2->ref_clk);
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+ if (!ref_clk_rate) {
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+ dev_err(dev, "Failed to get ref clock rate\n");
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+ err = -EINVAL;
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+ goto err_clk_off;
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+ }
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+
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+ usb2ctl = readl(dmu + BCMA_DMU_CRU_USB2_CONTROL);
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+
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+ if (usb2ctl & BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK) {
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+ usb_pll_pdiv = usb2ctl;
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+ usb_pll_pdiv &= BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK;
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+ usb_pll_pdiv >>= BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_SHIFT;
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+ } else {
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+ usb_pll_pdiv = 1 << 3;
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+ }
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+
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+ /* Calculate ndiv based on a solid 1920 MHz that is for USB2 PHY */
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+ usb_pll_ndiv = (1920000000 * usb_pll_pdiv) / ref_clk_rate;
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+
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+ /* Unlock DMU PLL settings with some magic value */
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+ writel(0x0000ea68, dmu + BCMA_DMU_CRU_CLKSET_KEY);
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+
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+ /* Write USB 2.0 PLL control setting */
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+ usb2ctl &= ~BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK;
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+ usb2ctl |= usb_pll_ndiv << BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT;
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+ writel(usb2ctl, dmu + BCMA_DMU_CRU_USB2_CONTROL);
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+
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+ /* Lock DMU PLL settings */
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+ writel(0x00000000, dmu + BCMA_DMU_CRU_CLKSET_KEY);
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+
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+err_clk_off:
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+ clk_disable_unprepare(usb2->ref_clk);
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+err_out:
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+ return err;
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+}
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+
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+static const struct phy_ops ops = {
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+ .init = bcm_ns_usb2_phy_init,
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+ .owner = THIS_MODULE,
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+};
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+
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+static int bcm_ns_usb2_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct bcm_ns_usb2 *usb2;
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+ struct resource *res;
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+ struct phy_provider *phy_provider;
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+
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+ usb2 = devm_kzalloc(&pdev->dev, sizeof(*usb2), GFP_KERNEL);
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+ if (!usb2)
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+ return -ENOMEM;
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+ usb2->dev = dev;
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+
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmu");
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+ usb2->dmu = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(usb2->dmu)) {
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+ dev_err(dev, "Failed to map DMU regs\n");
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+ return PTR_ERR(usb2->dmu);
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+ }
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+
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+ usb2->ref_clk = devm_clk_get(dev, "phy-ref-clk");
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+ if (IS_ERR(usb2->ref_clk)) {
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+ dev_err(dev, "Clock not defined\n");
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+ return PTR_ERR(usb2->ref_clk);
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+ }
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+
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+ usb2->phy = devm_phy_create(dev, NULL, &ops);
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+ if (IS_ERR(dev))
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+ return PTR_ERR(dev);
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+
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+ phy_set_drvdata(usb2->phy, usb2);
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+ platform_set_drvdata(pdev, usb2);
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+
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+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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+ return PTR_ERR_OR_ZERO(phy_provider);
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+}
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+
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+static const struct of_device_id bcm_ns_usb2_id_table[] = {
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+ { .compatible = "brcm,ns-usb2-phy", },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, bcm_ns_usb2_id_table);
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+
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+static struct platform_driver bcm_ns_usb2_driver = {
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+ .probe = bcm_ns_usb2_probe,
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+ .driver = {
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+ .name = "bcm_ns_usb2",
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+ .of_match_table = bcm_ns_usb2_id_table,
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+ },
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+};
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+module_platform_driver(bcm_ns_usb2_driver);
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+
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+MODULE_LICENSE("GPL v2");
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--- a/include/linux/bcma/bcma.h
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+++ b/include/linux/bcma/bcma.h
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@@ -4,6 +4,7 @@
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#include <linux/pci.h>
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#include <linux/mod_devicetable.h>
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+#include <linux/bcma/bcma_driver_arm_c9.h>
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#include <linux/bcma/bcma_driver_chipcommon.h>
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#include <linux/bcma/bcma_driver_pci.h>
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#include <linux/bcma/bcma_driver_pcie2.h>
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--- /dev/null
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+++ b/include/linux/bcma/bcma_driver_arm_c9.h
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@@ -0,0 +1,15 @@
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+#ifndef LINUX_BCMA_DRIVER_ARM_C9_H_
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+#define LINUX_BCMA_DRIVER_ARM_C9_H_
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+
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+/* DMU (Device Management Unit) */
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+#define BCMA_DMU_CRU_USB2_CONTROL 0x0164
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK 0x00000FFC
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT 2
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK 0x00007000
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+#define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_SHIFT 12
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+#define BCMA_DMU_CRU_CLKSET_KEY 0x0180
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+#define BCMA_DMU_CRU_STRAPS_CTRL 0x02A0
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+#define BCMA_DMU_CRU_STRAPS_CTRL_USB3 0x00000010
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+#define BCMA_DMU_CRU_STRAPS_CTRL_4BYTE 0x00008000
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+
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+#endif /* LINUX_BCMA_DRIVER_ARM_C9_H_ */
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