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9d7e603f4d
Some backported thermal patches ended up with the wrong kernel
version in their filename. Fix this.
Fixes: c36de2e73a ("mediatek: backport a hell of thermal commits")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
92 lines
2.9 KiB
Diff
92 lines
2.9 KiB
Diff
From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
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From: Frank Wunderlich <frank-w@public-files.de>
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Date: Fri, 22 Sep 2023 07:50:20 +0200
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Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
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support
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Add Support for Mediatek Filogic 880/MT7988 LVTS.
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
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---
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drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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--- a/drivers/thermal/mediatek/lvts_thermal.c
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+++ b/drivers/thermal/mediatek/lvts_thermal.c
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@@ -82,6 +82,8 @@
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#define LVTS_GOLDEN_TEMP_DEFAULT 50
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#define LVTS_COEFF_A_MT8195 -250460
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#define LVTS_COEFF_B_MT8195 250460
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+#define LVTS_COEFF_A_MT7988 -204650
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+#define LVTS_COEFF_B_MT7988 204650
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#define LVTS_MSR_IMMEDIATE_MODE 0
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#define LVTS_MSR_FILTERED_MODE 1
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@@ -89,6 +91,7 @@
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#define LVTS_MSR_READ_TIMEOUT_US 400
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#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
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+#define LVTS_HW_SHUTDOWN_MT7988 105000
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#define LVTS_HW_SHUTDOWN_MT8195 105000
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#define LVTS_MINIMUM_THRESHOLD 20000
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@@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_
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lvts_debugfs_exit(lvts_td);
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}
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+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
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+ {
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+ .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
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+ .lvts_sensor = {
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+ { .dt_id = MT7988_CPU_0 },
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+ { .dt_id = MT7988_CPU_1 },
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+ { .dt_id = MT7988_ETH2P5G_0 },
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+ { .dt_id = MT7988_ETH2P5G_1 }
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+ },
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+ .num_lvts_sensor = 4,
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+ .offset = 0x0,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
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+ },
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+ {
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+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
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+ .lvts_sensor = {
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+ { .dt_id = MT7988_TOPS_0},
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+ { .dt_id = MT7988_TOPS_1},
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+ { .dt_id = MT7988_ETHWARP_0},
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+ { .dt_id = MT7988_ETHWARP_1}
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+ },
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+ .num_lvts_sensor = 4,
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+ .offset = 0x100,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
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+ }
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+};
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+
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static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
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{
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.cal_offset = { 0x04, 0x07 },
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@@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819
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}
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};
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+static const struct lvts_data mt7988_lvts_ap_data = {
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+ .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
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+ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
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+ .temp_factor = LVTS_COEFF_A_MT7988,
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+ .temp_offset = LVTS_COEFF_B_MT7988,
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+};
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+
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static const struct lvts_data mt8195_lvts_mcu_data = {
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.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
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.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
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@@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt
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};
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static const struct of_device_id lvts_of_match[] = {
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+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
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{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
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{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
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{},
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