mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 17:01:14 +00:00
c2c741ccce
Initial backport of at803x PHY driver cleanup. This is in preparation for split and addition of new PHY Family based on at803x needed for ipq807x and other IPQ Series SoC. Other affected patch are automatically refreshed with make target/linux/refresh Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
56 lines
1.9 KiB
Diff
56 lines
1.9 KiB
Diff
From 723970affdd8766fa0d91cd34bf2ffc861538b5f Mon Sep 17 00:00:00 2001
|
|
From: Luo Jie <quic_luoj@quicinc.com>
|
|
Date: Sun, 16 Jul 2023 16:49:24 +0800
|
|
Subject: [PATCH 6/6] net: phy: at803x: add qca8081 fifo reset on the link
|
|
changed
|
|
|
|
The qca8081 sgmii fifo needs to be reset on link down and
|
|
released on the link up in case of any abnormal issue
|
|
such as the packet blocked on the PHY.
|
|
|
|
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
|
|
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
|
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
drivers/net/phy/at803x.c | 14 ++++++++++++++
|
|
1 file changed, 14 insertions(+)
|
|
|
|
--- a/drivers/net/phy/at803x.c
|
|
+++ b/drivers/net/phy/at803x.c
|
|
@@ -276,6 +276,9 @@
|
|
#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
|
|
#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
|
|
|
|
+#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
|
|
+#define QCA8081_PHY_FIFO_RSTN BIT(11)
|
|
+
|
|
MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
|
|
MODULE_AUTHOR("Matus Ujhelyi");
|
|
MODULE_LICENSE("GPL");
|
|
@@ -2037,6 +2040,16 @@ static int qca808x_get_features(struct p
|
|
return 0;
|
|
}
|
|
|
|
+static void qca808x_link_change_notify(struct phy_device *phydev)
|
|
+{
|
|
+ /* Assert interface sgmii fifo on link down, deassert it on link up,
|
|
+ * the interface device address is always phy address added by 1.
|
|
+ */
|
|
+ mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
|
|
+ MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
|
|
+ QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
|
|
+}
|
|
+
|
|
static struct phy_driver at803x_driver[] = {
|
|
{
|
|
/* Qualcomm Atheros AR8035 */
|
|
@@ -2213,6 +2226,7 @@ static struct phy_driver at803x_driver[]
|
|
.soft_reset = qca808x_soft_reset,
|
|
.cable_test_start = qca808x_cable_test_start,
|
|
.cable_test_get_status = qca808x_cable_test_get_status,
|
|
+ .link_change_notify = qca808x_link_change_notify,
|
|
}, };
|
|
|
|
module_phy_driver(at803x_driver);
|