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ca5c695a45
Deleted following upstreamed patches: bcm27xx: 950-0006-drm-vc4-hdmi-Fix-HPD-GPIO-detection.patch bcm27xx: 950-0420-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx: 950-0425-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx: 950-0432-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx: 950-0433-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx: 950-0435-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx: 950-0436-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx: 950-0437-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx: 950-0438-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx: 950-0443-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx: 950-0445-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch bcm27xx: 950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch bcm27xx: 950-0476-drm-vc4-Release-workaround-buffer-and-DMA-in-error-p.patch bcm27xx: 950-0477-drm-vc4-Correct-DSI-divider-calculations.patch bcm27xx: 950-0664-drm-vc4-dsi-Correct-max-divider-to-255-not-7.patch bcm53xx: 072-next-ARM_dts_BCM53015-add-mr26.patch mediatek: 920-linux-next-dts-mt7622-bpi-r64-fix-wps-button.patch Manually rebased following patches: bcm27xx: 950-0004-drm-vc4-hdmi-Remove-the-DDC-probing-for-status-detec.patch bcm27xx: 950-0700-net-phy-lan87xx-Decrease-phy-polling-rate.patch bcm27xx: 950-0711-drm-vc4-Rename-bridge-to-out_bridge.patch bcm27xx: 950-0713-drm-vc4-Remove-splitting-the-bridge-chain-from-the-d.patch bcm27xx: 950-0715-drm-vc4-Convert-vc4_dsi-to-using-a-bridge-instead-of.patch bcm27xx: 950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch bcm27xx: 950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch Runtime tested on turris-omnia and glinet-b1300. Tested-by: John Audia <therealgraysky@proton.me> [bcm2711/RPi4B, mt7622/RT3200] Signed-off-by: Petr Štetiar <ynezz@true.cz>
387 lines
7.6 KiB
Diff
387 lines
7.6 KiB
Diff
From 702a8f4744ed5b480f2b2411858184afdb10f9fd Mon Sep 17 00:00:00 2001
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From: Matthew Hagan <mnhagan88@gmail.com>
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Date: Fri, 6 Aug 2021 21:44:35 +0100
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Subject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX65 series
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MX65 & MX65W Hardware info:
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- CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz
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- RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)
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- Storage: 1 GB (Micron MT29F8G08ABACA)
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- Networking: BCM58625 switch (2x 1GbE ports)
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2x Qualcomm QCA8337 switches (10x 1GbE ports total)
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- PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12
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- USB: 1x USB2.0
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- Serial: Internal header
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- WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus.
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Note that a driver and firmware image for the BCM59111 PSE has been
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released under GPL, but this is not present in the kernel.
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Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/Makefile | 2 +
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arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++
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arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++
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arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++
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4 files changed, 337 insertions(+)
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create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
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create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts
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create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -162,6 +162,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
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bcm958625-meraki-mx64-a0.dtb \
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bcm958625-meraki-mx64w.dtb \
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bcm958625-meraki-mx64w-a0.dtb \
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+ bcm958625-meraki-mx65.dtb \
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+ bcm958625-meraki-mx65w.dtb \
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bcm958625hr.dtb \
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bcm988312hr.dtb \
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bcm958625k.dtb
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
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@@ -0,0 +1,279 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
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+ *
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+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
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+ */
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+
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+#include "bcm958625-meraki-mx6x-common.dtsi"
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+
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+/ {
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+ keys {
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+ compatible = "gpio-keys-polled";
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+ autorepeat;
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+ poll-interval = <20>;
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+
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+ reset {
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+ label = "reset";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led-0 {
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+ /* green:wan1-left */
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+ function = LED_FUNCTION_ACTIVITY;
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+ function-enumerator = <0>;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-1 {
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+ /* green:wan1-right */
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+ function = LED_FUNCTION_ACTIVITY;
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+ function-enumerator = <1>;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-2 {
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+ /* green:wan2-left */
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+ function = LED_FUNCTION_ACTIVITY;
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+ function-enumerator = <2>;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-3 {
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+ /* green:wan2-right */
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+ function = LED_FUNCTION_ACTIVITY;
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+ function-enumerator = <3>;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ led-4 {
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+ /* amber:power */
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+ function = LED_FUNCTION_POWER;
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+ color = <LED_COLOR_ID_AMBER>;
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+ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
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+ default-state = "on";
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+ };
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+
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+ led-5 {
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+ /* white:status */
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+ function = LED_FUNCTION_STATUS;
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+ color = <LED_COLOR_ID_WHITE>;
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+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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+ mdio-mii-mux {
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+ compatible = "mdio-mux-mmioreg";
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+ reg = <0x1803f1c0 0x4>;
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+ mux-mask = <0x2000>;
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+ mdio-parent-bus = <&mdio_ext>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mdio@0 {
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+ reg = <0x0>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ phy_port6: phy@0 {
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+ reg = <0>;
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+ };
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+
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+ phy_port7: phy@1 {
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+ reg = <1>;
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+ };
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+
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+ phy_port8: phy@2 {
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+ reg = <2>;
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+ };
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+
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+ phy_port9: phy@3 {
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+ reg = <3>;
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+ };
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+
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+ phy_port10: phy@4 {
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+ reg = <4>;
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+ };
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+
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+ switch@10 {
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+ compatible = "qca,qca8337";
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+ reg = <0x10>;
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+ dsa,member = <1 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ port@0 {
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+ reg = <0>;
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+ ethernet = <&sgmii1>;
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+ phy-mode = "sgmii";
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan8";
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+ phy-handle = <&phy_port6>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan9";
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+ phy-handle = <&phy_port7>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan10";
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+ phy-handle = <&phy_port8>;
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "lan11";
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+ phy-handle = <&phy_port9>;
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ label = "lan12";
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+ phy-handle = <&phy_port10>;
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+ };
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+ };
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+ };
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+ };
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+
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+ mdio-mii@2000 {
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+ reg = <0x2000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ phy_port1: phy@0 {
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+ reg = <0>;
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+ };
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+
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+ phy_port2: phy@1 {
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+ reg = <1>;
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+ };
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+
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+ phy_port3: phy@2 {
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+ reg = <2>;
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+ };
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+
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+ phy_port4: phy@3 {
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+ reg = <3>;
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+ };
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+
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+ phy_port5: phy@4 {
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+ reg = <4>;
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+ };
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+
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+ switch@10 {
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+ compatible = "qca,qca8337";
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+ reg = <0x10>;
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+ dsa,member = <2 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ port@0 {
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+ reg = <0>;
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+ ethernet = <&sgmii0>;
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+ phy-mode = "sgmii";
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan3";
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+ phy-handle = <&phy_port1>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan4";
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+ phy-handle = <&phy_port2>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan5";
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+ phy-handle = <&phy_port3>;
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "lan6";
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+ phy-handle = <&phy_port4>;
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ label = "lan7";
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+ phy-handle = <&phy_port5>;
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+ };
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&srab {
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+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
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+ status = "okay";
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+ dsa,member = <0 0>;
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+
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+ ports {
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+ port@0 {
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+ label = "wan1";
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+ reg = <0>;
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+ };
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+
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+ port@1 {
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+ label = "wan2";
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+ reg = <1>;
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+ };
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+
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+ sgmii0: port@4 {
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+ label = "sw0";
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+ reg = <4>;
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ sgmii1: port@5 {
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+ label = "sw1";
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+ reg = <5>;
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ port@8 {
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+ ethernet = <&amac2>;
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+ reg = <8>;
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts
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@@ -0,0 +1,24 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Device Tree Bindings for Cisco Meraki MX65.
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+ *
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+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
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+ */
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+
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+/dts-v1/;
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+
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+#include "bcm958625-meraki-alamo.dtsi"
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+
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+/ {
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+ model = "Cisco Meraki MX65";
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+ compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@60000000 {
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+ device_type = "memory";
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+ reg = <0x60000000 0x80000000>;
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
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@@ -0,0 +1,32 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Device Tree Bindings for Cisco Meraki MX65W.
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+ *
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+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
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+ */
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+
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+/dts-v1/;
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+
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+#include "bcm958625-meraki-alamo.dtsi"
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+
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+/ {
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+ model = "Cisco Meraki MX65W";
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+ compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@60000000 {
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+ device_type = "memory";
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+ reg = <0x60000000 0x80000000>;
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+ };
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+};
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+
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+&pcie0 {
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+ status = "okay";
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+};
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+
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+&pcie1 {
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+ status = "okay";
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+};
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