mirror of
https://github.com/openwrt/openwrt.git
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439 lines
9.8 KiB
Diff
439 lines
9.8 KiB
Diff
From 248d9a5b63bba72bfc316b8a48c6163fce5acc22 Mon Sep 17 00:00:00 2001
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From: Paulius Zaleckas <paulius.zaleckas@gmail.com>
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Date: Thu, 18 Feb 2010 21:53:01 +0200
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Subject: [PATCH] ARM: Use cache alignment from asm/cache.h
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Make code more optimal for ARM variants with
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different cache line size.
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Signed-off-by: Paulius Zaleckas <paulius.zaleckas@gmail.com>
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---
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arch/arm/boot/compressed/head.S | 11 ++++++-----
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arch/arm/include/asm/dma-mapping.h | 2 +-
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arch/arm/kernel/entry-armv.S | 31 ++++++++++++++++---------------
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arch/arm/kernel/entry-common.S | 7 ++++---
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arch/arm/kernel/head.S | 3 ++-
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arch/arm/kernel/vmlinux.lds.S | 5 +++--
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arch/arm/lib/copy_page.S | 2 +-
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arch/arm/lib/memchr.S | 3 ++-
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arch/arm/lib/memset.S | 3 ++-
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arch/arm/lib/memzero.S | 3 ++-
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arch/arm/lib/strchr.S | 3 ++-
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arch/arm/lib/strncpy_from_user.S | 3 ++-
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arch/arm/lib/strnlen_user.S | 3 ++-
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arch/arm/lib/strrchr.S | 3 ++-
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arch/arm/mm/abort-ev4.S | 3 ++-
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arch/arm/mm/abort-nommu.S | 3 ++-
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16 files changed, 51 insertions(+), 37 deletions(-)
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--- a/arch/arm/boot/compressed/head.S
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+++ b/arch/arm/boot/compressed/head.S
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@@ -9,6 +9,7 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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+#include <asm/cache.h>
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/*
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* Debugging stuff
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@@ -349,7 +350,7 @@ params: ldr r0, =0x10000100 @ params_p
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* This routine must preserve:
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* r4, r5, r6, r7, r8
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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cache_on: mov r3, #8 @ cache_on function
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b call_cache_fn
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@@ -537,7 +538,7 @@ __common_mmu_cache_on:
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mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c3, c0, 0 @ load domain access control
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b 1f
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- .align 5 @ cache line aligned
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+ .align L1_CACHE_SHIFT @ cache line aligned
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1: mcr p15, 0, r0, c1, c0, 0 @ load control register
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mrc p15, 0, r0, c1, c0, 0 @ and read it back to
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sub pc, lr, r0, lsr #32 @ properly flush pipeline
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@@ -556,7 +557,7 @@ __common_mmu_cache_on:
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* r8 = atags pointer
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* r9-r12,r14 = corrupted
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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reloc_start: add r9, r5, r0
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sub r9, r9, #128 @ do not copy the stack
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debug_reloc_start
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@@ -786,7 +787,7 @@ proc_types:
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* This routine must preserve:
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* r4, r6, r7
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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cache_off: mov r3, #12 @ cache_off function
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b call_cache_fn
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@@ -861,7 +862,7 @@ __armv3_mmu_cache_off:
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* This routine must preserve:
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* r0, r4, r5, r6, r7
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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cache_clean_flush:
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mov r3, #16
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b call_cache_fn
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--- a/arch/arm/kernel/entry-armv.S
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+++ b/arch/arm/kernel/entry-armv.S
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@@ -23,6 +23,7 @@
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#include <asm/unwind.h>
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#include <asm/unistd.h>
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#include <asm/tls.h>
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+#include <asm/cache.h>
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#include "entry-header.S"
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@@ -165,7 +166,7 @@ ENDPROC(__und_invalid)
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stmia r5, {r0 - r4}
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.endm
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- .align 5
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+ .align L1_CACHE_SHIFT
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__dabt_svc:
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svc_entry
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@@ -213,7 +214,7 @@ __dabt_svc:
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UNWIND(.fnend )
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ENDPROC(__dabt_svc)
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- .align 5
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+ .align L1_CACHE_SHIFT
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__irq_svc:
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svc_entry
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@@ -257,7 +258,7 @@ svc_preempt:
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b 1b
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#endif
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- .align 5
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+ .align L1_CACHE_SHIFT
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__und_svc:
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#ifdef CONFIG_KPROBES
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@ If a kprobe is about to simulate a "stmdb sp..." instruction,
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@@ -303,7 +304,7 @@ __und_svc:
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UNWIND(.fnend )
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ENDPROC(__und_svc)
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- .align 5
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+ .align L1_CACHE_SHIFT
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__pabt_svc:
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svc_entry
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@@ -339,7 +340,7 @@ __pabt_svc:
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UNWIND(.fnend )
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ENDPROC(__pabt_svc)
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- .align 5
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+ .align L1_CACHE_SHIFT
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.LCcralign:
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.word cr_alignment
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#ifdef MULTI_DABORT
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@@ -412,7 +413,7 @@ ENDPROC(__pabt_svc)
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#endif
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.endm
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- .align 5
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+ .align L1_CACHE_SHIFT
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__dabt_usr:
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usr_entry
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kuser_cmpxchg_check
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@@ -444,7 +445,7 @@ __dabt_usr:
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UNWIND(.fnend )
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ENDPROC(__dabt_usr)
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- .align 5
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+ .align L1_CACHE_SHIFT
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__irq_usr:
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usr_entry
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kuser_cmpxchg_check
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@@ -473,7 +474,7 @@ ENDPROC(__irq_usr)
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.ltorg
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- .align 5
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+ .align L1_CACHE_SHIFT
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__und_usr:
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usr_entry
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@@ -689,7 +690,7 @@ __und_usr_unknown:
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b do_undefinstr
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ENDPROC(__und_usr_unknown)
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- .align 5
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+ .align L1_CACHE_SHIFT
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__pabt_usr:
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usr_entry
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@@ -803,7 +804,7 @@ ENDPROC(__switch_to)
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#endif
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.endm
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- .align 5
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+ .align L1_CACHE_SHIFT
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.globl __kuser_helper_start
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__kuser_helper_start:
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@@ -843,7 +844,7 @@ __kuser_memory_barrier: @ 0xffff0fa0
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smp_dmb
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usr_ret lr
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- .align 5
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+ .align L1_CACHE_SHIFT
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/*
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* Reference prototype:
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@@ -973,7 +974,7 @@ kuser_cmpxchg_fixup:
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#endif
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- .align 5
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+ .align L1_CACHE_SHIFT
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/*
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* Reference prototype:
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@@ -1051,7 +1052,7 @@ __kuser_helper_end:
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* of which is copied into r0 for the mode specific abort handler.
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*/
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.macro vector_stub, name, mode, correction=0
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- .align 5
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+ .align L1_CACHE_SHIFT
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vector_\name:
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.if \correction
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@@ -1182,7 +1183,7 @@ __stubs_start:
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.long __und_invalid @ e
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.long __und_invalid @ f
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- .align 5
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+ .align L1_CACHE_SHIFT
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/*=============================================================================
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* Undefined FIQs
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@@ -1212,7 +1213,7 @@ vector_addrexcptn:
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* We group all the following data together to optimise
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* for CPUs with separate I & D caches.
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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.LCvswi:
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.word vector_swi
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--- a/arch/arm/kernel/entry-common.S
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+++ b/arch/arm/kernel/entry-common.S
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@@ -10,13 +10,14 @@
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#include <asm/unistd.h>
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#include <asm/ftrace.h>
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+#include <asm/cache.h>
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#include <mach/entry-macro.S>
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#include <asm/unwind.h>
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#include "entry-header.S"
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- .align 5
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+ .align L1_CACHE_SHIFT
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/*
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* This is the fast syscall return path. We do as little as
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* possible here, and this includes saving r0 back into the SVC
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@@ -221,7 +222,7 @@ ftrace_stub:
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#define A710(code...)
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#endif
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- .align 5
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+ .align L1_CACHE_SHIFT
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ENTRY(vector_swi)
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0 - r12
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@@ -354,7 +355,7 @@ __sys_trace_return:
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bl syscall_trace
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b ret_slow_syscall
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- .align 5
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+ .align L1_CACHE_SHIFT
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#ifdef CONFIG_ALIGNMENT_TRAP
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.type __cr_alignment, #object
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__cr_alignment:
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--- a/arch/arm/kernel/head.S
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+++ b/arch/arm/kernel/head.S
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@@ -21,6 +21,7 @@
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/system.h>
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+#include <asm/cache.h>
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#if (PHYS_OFFSET & 0x001fffff)
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#error "PHYS_OFFSET must be at an even 2MiB boundary!"
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@@ -192,7 +193,7 @@ ENDPROC(__enable_mmu)
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*
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* other registers depend on the function called upon completion
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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__turn_mmu_on:
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mov r0, r0
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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--- a/arch/arm/kernel/vmlinux.lds.S
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+++ b/arch/arm/kernel/vmlinux.lds.S
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@@ -7,6 +7,7 @@
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/page.h>
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+#include <asm/cache.h>
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OUTPUT_ARCH(arm)
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ENTRY(stext)
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--- a/arch/arm/lib/copy_page.S
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+++ b/arch/arm/lib/copy_page.S
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@@ -17,7 +17,7 @@
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#define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 ))
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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/*
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* StrongARM optimised copy_page routine
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* now 1.78bytes/cycle, was 1.60 bytes/cycle (50MHz bus -> 89MB/s)
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--- a/arch/arm/lib/memchr.S
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+++ b/arch/arm/lib/memchr.S
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@@ -11,9 +11,10 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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+#include <asm/cache.h>
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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ENTRY(memchr)
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1: subs r2, r2, #1
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bmi 2f
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--- a/arch/arm/lib/memset.S
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+++ b/arch/arm/lib/memset.S
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@@ -11,9 +11,10 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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+#include <asm/cache.h>
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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.word 0
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1: subs r2, r2, #4 @ 1 do we have enough
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--- a/arch/arm/lib/memzero.S
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+++ b/arch/arm/lib/memzero.S
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@@ -9,9 +9,10 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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+#include <asm/cache.h>
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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.word 0
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/*
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* Align the pointer in r0. r3 contains the number of bytes that we are
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--- a/arch/arm/lib/strchr.S
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+++ b/arch/arm/lib/strchr.S
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@@ -11,9 +11,10 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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+#include <asm/cache.h>
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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ENTRY(strchr)
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and r1, r1, #0xff
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1: ldrb r2, [r0], #1
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--- a/arch/arm/lib/strncpy_from_user.S
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+++ b/arch/arm/lib/strncpy_from_user.S
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@@ -10,9 +10,10 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/errno.h>
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+#include <asm/cache.h>
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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/*
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* Copy a string from user space to kernel space.
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--- a/arch/arm/lib/strnlen_user.S
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+++ b/arch/arm/lib/strnlen_user.S
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@@ -10,9 +10,10 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/errno.h>
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+#include <asm/cache.h>
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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/* Prototype: unsigned long __strnlen_user(const char *str, long n)
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* Purpose : get length of a string in user memory
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--- a/arch/arm/lib/strrchr.S
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+++ b/arch/arm/lib/strrchr.S
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@@ -11,9 +11,10 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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+#include <asm/cache.h>
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.text
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- .align 5
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+ .align L1_CACHE_SHIFT
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ENTRY(strrchr)
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mov r3, #0
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1: ldrb r2, [r0], #1
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--- a/arch/arm/mm/abort-ev4.S
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+++ b/arch/arm/mm/abort-ev4.S
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@@ -1,5 +1,6 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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+#include <asm/cache.h>
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/*
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* Function: v4_early_abort
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*
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@@ -17,7 +18,7 @@
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* abort here if the I-TLB and D-TLB aren't seeing the same
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* picture. Unfortunately, this does happen. We live with it.
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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ENTRY(v4_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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--- a/arch/arm/mm/abort-nommu.S
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+++ b/arch/arm/mm/abort-nommu.S
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@@ -1,5 +1,6 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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+#include <asm/cache.h>
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/*
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* Function: nommu_early_abort
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*
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@@ -12,7 +13,7 @@
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* Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
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* Just fill zero into the registers.
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*/
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- .align 5
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+ .align L1_CACHE_SHIFT
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ENTRY(nommu_early_abort)
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mov r0, #0 @ clear r0, r1 (no FSR/FAR)
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mov r1, #0
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