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ce1de42096
For some reason LS1012A and LS1046A devboards don't work well with
Spansion SPI NOR flash. It cause read and write errors like:
[ 27.285887] jffs2: Newly-erased block contained word 0xc20031985 at offset 0x025ae000
[ 27.468922] jffs2: Newly-erased block contained word 0x0 at offset 0x02573000
[ 27.502615] jffs2: Newly-erased block contained word 0xe723f41e5823f110 at offset 0x02572000
[ 27.541550] jffs2: Newly-erased block contained word 0x1a7d266ee6 at offset 0x02571000
[ 27.577195] jffs2: Newly-erased block contained word 0x5d000bae8d52fec6 at offset 0x02570000
[ 27.611800] jffs2: Newly-erased block contained word 0x63515aee63515a4b at offset 0x0256f000
[ 27.651749] jffs2: Newly-erased block contained word 0xc20031985 at offset 0x0256e000
[ 27.825593] jffs2: Newly-erased block contained word 0xc20031985 at offset 0x0252e000
NXP have found workarround and applied in their vendor kernel version.
They force 1x tx and 1x rx lines in qspi. That method fix issues.
This patch ports patches from NXP LSDK tree.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
(cherry picked from commit 2e4fe289ce)
30 lines
858 B
Diff
30 lines
858 B
Diff
From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
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From: Kuldeep Singh <kuldeep.singh@nxp.com>
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Date: Tue, 7 Jan 2020 17:14:32 +0530
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Subject: [PATCH] arm64: dts: ls1012a-rdb: workaround by updating qspi flash to
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single mode
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Update rx and tx bus-width to 1 to use single mode to workaround ubifs
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issue found with double mode.
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[ Leo: Local workaround ]
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Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
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@@ -92,8 +92,8 @@
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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reg = <0>;
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- spi-rx-bus-width = <2>;
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- spi-tx-bus-width = <2>;
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+ spi-rx-bus-width = <1>;
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+ spi-tx-bus-width = <1>;
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};
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};
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