mirror of
https://github.com/openwrt/openwrt.git
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a696e325f7
All patches automatically rebased.
Build system: x86_64
Build-tested: ramips/mt7621*
*FS#4149 affects me so I had to revert 7f1edbd412
in order to downgrade to 2.35.1
Signed-off-by: John Audia <graysky@archlinux.us>
164 lines
5.8 KiB
Diff
164 lines
5.8 KiB
Diff
From c6f39379529e74eccbe317e70bb11d18110c63d4 Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Sat, 9 Nov 2019 15:03:00 +0200
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Subject: [PATCH] net: mscc: ocelot: split assignment of the cpu port into a
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separate function
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Now that the places that configure routing destinations for the CPU port
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have been marked as such, allow callers to specify their own CPU port
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that is different than ocelot->num_phys_ports. A user will be the Felix
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DSA driver, where the CPU port is one of the physical ports (NPI mode).
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mscc/ocelot.c | 65 +++++++++++++++++++++-----------
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drivers/net/ethernet/mscc/ocelot.h | 12 ++++++
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drivers/net/ethernet/mscc/ocelot_board.c | 2 +
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3 files changed, 57 insertions(+), 22 deletions(-)
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--- a/drivers/net/ethernet/mscc/ocelot.c
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+++ b/drivers/net/ethernet/mscc/ocelot.c
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@@ -380,12 +380,6 @@ static void ocelot_vlan_init(struct ocel
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ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
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ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
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- /* Configure the CPU port to be VLAN aware */
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- ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
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- ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
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- ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
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- ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
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-
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/* Set vlan ingress filter mask to all ports but the CPU port by
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* default.
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*/
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@@ -2223,11 +2217,52 @@ int ocelot_probe_port(struct ocelot *oce
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}
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EXPORT_SYMBOL(ocelot_probe_port);
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+void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
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+ enum ocelot_tag_prefix injection,
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+ enum ocelot_tag_prefix extraction)
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+{
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+ /* Configure and enable the CPU port. */
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+ ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
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+ ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
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+ ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
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+ ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
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+ ANA_PORT_PORT_CFG, cpu);
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+
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+ /* If the CPU port is a physical port, set up the port in Node
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+ * Processor Interface (NPI) mode. This is the mode through which
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+ * frames can be injected from and extracted to an external CPU.
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+ * Only one port can be an NPI at the same time.
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+ */
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+ if (cpu < ocelot->num_phys_ports) {
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+ ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
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+ QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
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+ QSYS_EXT_CPU_CFG);
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+ }
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+
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+ /* CPU port Injection/Extraction configuration */
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+ ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
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+ QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
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+ QSYS_SWITCH_PORT_MODE_PORT_ENA,
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+ QSYS_SWITCH_PORT_MODE, cpu);
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+ ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) |
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+ SYS_PORT_MODE_INCL_INJ_HDR(injection),
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+ SYS_PORT_MODE, cpu);
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+
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+ /* Configure the CPU port to be VLAN aware */
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+ ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
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+ ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
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+ ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
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+ ANA_PORT_VLAN_CFG, cpu);
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+
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+ ocelot->cpu = cpu;
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+}
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+EXPORT_SYMBOL(ocelot_set_cpu_port);
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+
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int ocelot_init(struct ocelot *ocelot)
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{
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- u32 port;
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- int i, ret, cpu = ocelot->num_phys_ports;
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char queue_name[32];
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+ int i, ret;
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+ u32 port;
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ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
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sizeof(u32), GFP_KERNEL);
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@@ -2307,13 +2342,6 @@ int ocelot_init(struct ocelot *ocelot)
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ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
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}
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- /* Configure and enable the CPU port. */
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- ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
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- ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
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- ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
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- ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
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- ANA_PORT_PORT_CFG, cpu);
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-
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/* Allow broadcast MAC frames. */
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for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
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u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
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@@ -2326,13 +2354,6 @@ int ocelot_init(struct ocelot *ocelot)
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ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
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ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
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- /* CPU port Injection/Extraction configuration */
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- ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
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- QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
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- QSYS_SWITCH_PORT_MODE_PORT_ENA,
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- QSYS_SWITCH_PORT_MODE, cpu);
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- ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
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- SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
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/* Allow manual injection via DEVCPU_QS registers, and byte swap these
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* registers endianness.
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*/
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--- a/drivers/net/ethernet/mscc/ocelot.h
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+++ b/drivers/net/ethernet/mscc/ocelot.h
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@@ -427,6 +427,13 @@ struct ocelot_multicast {
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u16 ports;
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};
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+enum ocelot_tag_prefix {
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+ OCELOT_TAG_PREFIX_DISABLED = 0,
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+ OCELOT_TAG_PREFIX_NONE,
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+ OCELOT_TAG_PREFIX_SHORT,
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+ OCELOT_TAG_PREFIX_LONG,
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+};
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+
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struct ocelot_port;
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struct ocelot_stat_layout {
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@@ -455,6 +462,7 @@ struct ocelot {
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u8 num_phys_ports;
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u8 num_cpu_ports;
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+ u8 cpu;
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struct ocelot_port **ports;
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u32 *lags;
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@@ -552,6 +560,10 @@ int ocelot_probe_port(struct ocelot *oce
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void __iomem *regs,
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struct phy_device *phy);
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+void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
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+ enum ocelot_tag_prefix injection,
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+ enum ocelot_tag_prefix extraction);
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+
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extern struct notifier_block ocelot_netdevice_nb;
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extern struct notifier_block ocelot_switchdev_nb;
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extern struct notifier_block ocelot_switchdev_blocking_nb;
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--- a/drivers/net/ethernet/mscc/ocelot_board.c
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+++ b/drivers/net/ethernet/mscc/ocelot_board.c
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@@ -373,6 +373,8 @@ static int mscc_ocelot_probe(struct plat
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sizeof(struct ocelot_port *), GFP_KERNEL);
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ocelot_init(ocelot);
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+ ocelot_set_cpu_port(ocelot, ocelot->num_phys_ports,
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+ OCELOT_TAG_PREFIX_NONE, OCELOT_TAG_PREFIX_NONE);
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for_each_available_child_of_node(ports, portnp) {
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struct ocelot_port_private *priv;
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