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02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
153 lines
4.4 KiB
Diff
153 lines
4.4 KiB
Diff
From 49134da893bc11e833e3d87139c57e3b84e65219 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Thu, 19 Jun 2014 18:46:31 -0700
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Subject: [PATCH 167/182] clk: qcom: Add HFPLL driver
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On some devices (MSM8974 for example), the HFPLLs are
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instantiated within the Krait processor subsystem as separate
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register regions. Add a driver for these PLLs so that we can
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provide HFPLL clocks for use by the system.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/Kconfig | 8 ++++
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/hfpll.c | 110 +++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 119 insertions(+)
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create mode 100644 drivers/clk/qcom/hfpll.c
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -53,3 +53,11 @@ config MSM_MMCC_8974
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Support for the multimedia clock controller on msm8974 devices.
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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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+
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+config QCOM_HFPLL
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+ tristate "High-Frequency PLL (HFPLL) Clock Controller"
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+ depends on COMMON_CLK_QCOM
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+ help
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+ Support for the high-frequency PLLs present on Qualcomm devices.
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+ Say Y if you want to support CPU frequency scaling on devices
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+ such as MSM8974, APQ8084, etc.
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -16,3 +16,4 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm896
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obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
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obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
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obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
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--- /dev/null
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+++ b/drivers/clk/qcom/hfpll.c
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@@ -0,0 +1,110 @@
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+/*
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+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/of.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+#include <linux/regmap.h>
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+
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+#include "clk-regmap.h"
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+#include "clk-hfpll.h"
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+
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+static const struct hfpll_data hdata = {
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+ .mode_reg = 0x00,
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+ .l_reg = 0x04,
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+ .m_reg = 0x08,
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+ .n_reg = 0x0c,
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+ .user_reg = 0x10,
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+ .config_reg = 0x14,
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+ .config_val = 0x430405d,
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+ .status_reg = 0x1c,
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+ .lock_bit = 16,
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+
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+ .user_val = 0x8,
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+ .user_vco_mask = 0x100000,
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+ .low_vco_max_rate = 1248000000,
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+ .min_rate = 537600000UL,
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+ .max_rate = 2900000000UL,
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+};
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+
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+static const struct of_device_id qcom_hfpll_match_table[] = {
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+ { .compatible = "qcom,hfpll" },
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+ { }
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+};
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+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
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+
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+static struct regmap_config hfpll_regmap_config = {
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+ .reg_bits = 32,
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+ .reg_stride = 4,
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+ .val_bits = 32,
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+ .max_register = 0x30,
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+ .fast_io = true,
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+};
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+
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+static int qcom_hfpll_probe(struct platform_device *pdev)
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+{
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+ struct clk *clk;
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+ struct resource *res;
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+ struct device *dev = &pdev->dev;
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+ void __iomem *base;
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+ struct regmap *regmap;
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+ struct clk_hfpll *h;
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+ struct clk_init_data init = {
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+ .parent_names = (const char *[]){ "xo" },
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+ .num_parents = 1,
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+ .ops = &clk_ops_hfpll,
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+ };
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+
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+ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
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+ if (!h)
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+ return -ENOMEM;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ base = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ if (of_property_read_string_index(dev->of_node, "clock-output-names",
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+ 0, &init.name))
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+ return -ENODEV;
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+
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+ h->d = &hdata;
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+ h->clkr.hw.init = &init;
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+ spin_lock_init(&h->lock);
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+
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+ clk = devm_clk_register_regmap(&pdev->dev, &h->clkr);
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+
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+ return PTR_ERR_OR_ZERO(clk);
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+}
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+
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+static struct platform_driver qcom_hfpll_driver = {
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+ .probe = qcom_hfpll_probe,
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+ .driver = {
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+ .name = "qcom-hfpll",
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+ .owner = THIS_MODULE,
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+ .of_match_table = qcom_hfpll_match_table,
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+ },
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+};
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+module_platform_driver(qcom_hfpll_driver);
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+
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+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
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+MODULE_LICENSE("GPL v2");
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+MODULE_ALIAS("platform:qcom-hfpll");
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