mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
6ec7711d00
Make all the patches apply. This also refreshes some of the kernel configurations. Signed-off-by: Martin Schiller <ms@dev.tdt.de>
41 lines
1.1 KiB
Diff
41 lines
1.1 KiB
Diff
From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001
|
|
From: Mathias Kresin <openwrt@kresin.me>
|
|
Date: Mon, 2 May 2016 18:50:00 +0000
|
|
Subject: [PATCH] xrx200: add gphy clk src device tree binding
|
|
|
|
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
|
|
---
|
|
arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++
|
|
1 file changed, 16 insertions(+)
|
|
|
|
--- a/arch/mips/lantiq/xway/sysctrl.c
|
|
+++ b/arch/mips/lantiq/xway/sysctrl.c
|
|
@@ -439,6 +439,20 @@ static void clkdev_add_clkout(void)
|
|
}
|
|
}
|
|
|
|
+static void set_phy_clock_source(struct device_node *np_cgu)
|
|
+{
|
|
+ u32 phy_clk_src, ifcc;
|
|
+
|
|
+ if (!np_cgu)
|
|
+ return;
|
|
+
|
|
+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
|
|
+ return;
|
|
+
|
|
+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
|
|
+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
|
|
+}
|
|
+
|
|
/* bring up all register ranges that we need for basic system control */
|
|
void __init ltq_soc_init(void)
|
|
{
|
|
@@ -608,4 +622,6 @@ void __init ltq_soc_init(void)
|
|
clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
|
|
}
|
|
usb_set_clock();
|
|
+
|
|
+ set_phy_clock_source(np_cgu);
|
|
}
|