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55be011a71
This backports GD SPI NAND support from nand/next to v5.10 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
92 lines
3.8 KiB
Diff
92 lines
3.8 KiB
Diff
From 54647cd003c08b714474a5b599a147ec6a160486 Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Sun, 20 Mar 2022 18:00:01 +0800
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Subject: [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG
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Add support for:
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GD5F{1,2}GM7{U,R}ExxG
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GD5F4GM8{U,R}ExxG
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These are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice
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with 8b/512b on-die ECC capability.
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These chips (and currently supported GD5FxGQ5 chips) have QIO DTR
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instruction for reading page cache. It isn't added in this patch because
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I don't have a DTR spi controller for testing.
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.com
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---
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drivers/mtd/nand/spi/gigadevice.c | 60 +++++++++++++++++++++++++++++++
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1 file changed, 60 insertions(+)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -441,6 +441,66 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq5xexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GM7UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GM7RExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GM7UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F2GM7RExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
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+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GM8UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
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+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F4GM8RExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
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+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
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+ NAND_ECCREQ(8, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq4uexxg_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
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