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f31ab2abef
Some VRX518 modems fail to initialize properly with the error message
"dc_ep_clk_on failed". As a result, the DSL data path doesn't work.
This hack, which is based on code from the FRITZ!Box 7530 GPL archive,
fixes the issue. It changes the PCIe vendor/device ID to values matching
a Lantiq SoC. It also appears to emulate a Lantiq CPU ID register for
connected PCIe devices, by remapping the matching address area to a
specially crafted buffer using the address translation unit.
A dedicated compatible is created to activate this in
the device tree, so this shouldn't affect any devices other than
FRITZ!Box 7530/7520.
Original investigation was done in 59f5212517 which used the "avm,host_magic" property to enabled the patch.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Florian Maurer <f.maurer@outlook.de>
Link: https://github.com/openwrt/openwrt/pull/17622
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 676dcb1b2cf84142a61d51a15e7a8e1bdc937c23)
167 lines
6.0 KiB
Diff
167 lines
6.0 KiB
Diff
From f4f03dca92b45616ef0325051fdc7627c16fdd62 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 7 May 2024 20:21:17 +0200
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Subject: [PATCH] PCI: qcom: add hack compatible for ipq4019 Lantiq DSL
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Add hack compatible for ipq4019 Lantiq DSL
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This change the PCIe vendor/device ID to the values from Lantiq
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GRX500 SoCs. We also program the ATU to fake the CPU ID as a Lantiq CPU
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by providing to the Lantiq firmware custom crafted value in the address
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the firmware would expect the CPU ID to be readable.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Florian Maurer <f.maurer@outlook.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 94 +++++++++++++++++++++++++-
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1 file changed, 93 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -184,11 +184,24 @@ struct qcom_pcie_resources_2_3_3 {
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#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
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#define QCOM_PCIE_2_4_0_MAX_RESETS 12
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+/*
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+ * This value is the manufacturer ID of Lantiq. The address where
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+ * it will be visible for the PCIe device matches the location of
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+ * CPU ID registers on Lantiq SocS (MPS base address is 0x1f107000).
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+ */
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+#define QCOM_PCIE_2_4_0_CPU_ID_BASE_REG 0x1f107000
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+#define QCOM_PCIE_2_4_0_CPU_ID_REG 0x340
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+#define QCOM_PCIE_2_4_0_CPU_ID_REG_OFFSET (QCOM_PCIE_2_4_0_CPU_ID_REG / sizeof(u32))
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+#define QCOM_PCIE_2_4_0_CPU_ID_REG_VAL (0x389 << 5)
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+#define QCOM_PCIE_2_4_0_GRX500_VENDOR_ID 0x1bef
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+#define QCOM_PCIE_2_4_0_GRX500_DEVICE_ID 0x0030
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struct qcom_pcie_resources_2_4_0 {
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struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
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int num_clks;
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struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS];
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int num_resets;
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+ void *lantiq_hack_virt;
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+ dma_addr_t lantiq_hack_phys;
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};
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#define QCOM_PCIE_2_7_0_MAX_CLOCKS 15
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@@ -629,12 +642,65 @@ static int qcom_pcie_post_init_2_3_2(str
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return 0;
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}
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+static void qcom_pcie_host_post_init_2_3_2_lantiq_hack(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
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+ struct dw_pcie *pci = pcie->pci;
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+ struct dw_pcie_rp *pp = &pci->pp;
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+ struct device *dev = pci->dev;
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+ struct resource_entry *entry;
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+ int ret, index = 0;
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+ u64 addr, phys;
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+ u32 *val;
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+
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+ res->lantiq_hack_virt = dma_alloc_coherent(dev, SZ_4K,
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+ &res->lantiq_hack_phys,
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+ GFP_ATOMIC);
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+ if (!res->lantiq_hack_virt) {
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+ dev_err(dev, "failed to allocate DMA for lantiq hack\n");
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+ return;
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+ }
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+
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+ /* Fake Lantiq CPU ID register */
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+ val = (u32 *)res->lantiq_hack_virt;
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+ val[QCOM_PCIE_2_4_0_CPU_ID_REG_OFFSET] = QCOM_PCIE_2_4_0_CPU_ID_REG_VAL;
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+
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+ /* Increment index based on used iATU */
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+ resource_list_for_each_entry(entry, &pp->bridge->dma_ranges)
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+ if (resource_type(entry->res) == IORESOURCE_MEM)
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+ index++;
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+
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+ /* Check if there is space for an additional iATU */
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+ if (index >= pci->num_ib_windows) {
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+ dev_err(dev, "No inbound iATU window available for magic\n");
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+ return;
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+ }
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+
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+ addr = QCOM_PCIE_2_4_0_CPU_ID_BASE_REG;
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+ phys = res->lantiq_hack_phys;
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+
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+ /* Make it visible to PCIe devices using address translation unit */
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+ ret = dw_pcie_prog_inbound_atu(pci, index, PCIE_ATU_TYPE_MEM,
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+ phys, addr, SZ_4K);
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+ if (ret) {
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+ dev_err(dev, "timeout waiting for IATU for lantiq hack: %d\n", ret);
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+ return;
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+ }
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+
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+ /* Set vendor/device ID of GRX500 PCIe host */
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+ dw_pcie_dbi_ro_wr_en(pci);
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+ dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, QCOM_PCIE_2_4_0_GRX500_VENDOR_ID);
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+ dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, QCOM_PCIE_2_4_0_GRX500_DEVICE_ID);
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+ dw_pcie_dbi_ro_wr_dis(pci);
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+}
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+
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static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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- bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
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+ bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019") ||
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+ of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019-lantiq-hack");
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int ret;
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res->clks[0].id = "aux";
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@@ -679,6 +745,17 @@ static void qcom_pcie_deinit_2_4_0(struc
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clk_bulk_disable_unprepare(res->num_clks, res->clks);
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}
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+static void qcom_pcie_deinit_2_4_0_lantiq_hack(struct qcom_pcie *pcie)
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+{
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+ struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
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+ struct dw_pcie *pci = pcie->pci;
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+ struct device *dev = pci->dev;
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+
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+ dma_free_coherent(dev, SZ_4K, res->lantiq_hack_virt, res->lantiq_hack_phys);
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+
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+ qcom_pcie_deinit_2_4_0(pcie);
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+}
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+
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static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
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@@ -1292,6 +1369,16 @@ static const struct qcom_pcie_ops ops_2_
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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};
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+/* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a Lantiq DSL Hack */
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+static const struct qcom_pcie_ops ops_2_4_0_lantiq_hack = {
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+ .get_resources = qcom_pcie_get_resources_2_4_0,
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+ .init = qcom_pcie_init_2_4_0,
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+ .post_init = qcom_pcie_post_init_2_3_2,
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+ .host_post_init = qcom_pcie_host_post_init_2_3_2_lantiq_hack,
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+ .deinit = qcom_pcie_deinit_2_4_0_lantiq_hack,
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+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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+};
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+
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/* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
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static const struct qcom_pcie_ops ops_2_3_3 = {
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.get_resources = qcom_pcie_get_resources_2_3_3,
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@@ -1354,6 +1441,10 @@ static const struct qcom_pcie_cfg cfg_2_
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.ops = &ops_2_4_0,
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};
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+static const struct qcom_pcie_cfg cfg_2_4_0_lantiq_hack = {
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+ .ops = &ops_2_4_0_lantiq_hack,
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+};
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+
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static const struct qcom_pcie_cfg cfg_2_7_0 = {
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.ops = &ops_2_7_0,
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};
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@@ -1641,6 +1732,7 @@ static const struct of_device_id qcom_pc
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{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
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{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
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{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
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+ { .compatible = "qcom,pcie-ipq4019-lantiq-hack", .data = &cfg_2_4_0_lantiq_hack },
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{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
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{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
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{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
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