mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 00:11:13 +00:00
0171157d45
The patches were generated from the RPi repo with the following command: git format-patch v6.6.44..rpi-6.6.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
27 lines
1.1 KiB
Diff
27 lines
1.1 KiB
Diff
From e9294823cf02068189a0e901223ed4991923c689 Mon Sep 17 00:00:00 2001
|
|
From: Phil Elwell <phil@raspberrypi.com>
|
|
Date: Wed, 31 Jul 2024 10:55:19 +0100
|
|
Subject: [PATCH 1202/1215] spi: dw: Clamp the minimum clock speed
|
|
|
|
The DW SPI interface has a 16-bit clock divider, where the bottom bit
|
|
of the divisor must be 0. Limit how low the clock speed can go to
|
|
prevent the clock divider from being truncated, as that could lead to
|
|
a much higher clock rate than requested.
|
|
|
|
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
|
|
---
|
|
drivers/spi/spi-dw-core.c | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
--- a/drivers/spi/spi-dw-core.c
|
|
+++ b/drivers/spi/spi-dw-core.c
|
|
@@ -397,7 +397,7 @@ void dw_spi_update_config(struct dw_spi
|
|
dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0);
|
|
|
|
/* Note DW APB SSI clock divider doesn't support odd numbers */
|
|
- clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe;
|
|
+ clk_div = min(DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1, 0xfffe) & 0xfffe;
|
|
speed_hz = dws->max_freq / clk_div;
|
|
|
|
if (dws->current_freq != speed_hz) {
|