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The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
43 lines
1.2 KiB
Diff
43 lines
1.2 KiB
Diff
From 1b23a4e0f03063f823ea38065c1106f62a56b408 Mon Sep 17 00:00:00 2001
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From: Mingkai Hu <mingkai.hu@nxp.com>
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Date: Mon, 7 Nov 2016 15:03:51 +0800
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Subject: [PATCH 230/238] layerscape/pci: fix linkup issue
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commit e6612d785198abbb39142e2acb63f9bff26ab718
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[context adjustment]
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Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
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Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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drivers/pci/host/pci-layerscape.c | 13 +++++++++----
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1 file changed, 9 insertions(+), 4 deletions(-)
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diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
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index 00feabf..f85ebcf 100644
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--- a/drivers/pci/host/pci-layerscape.c
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+++ b/drivers/pci/host/pci-layerscape.c
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@@ -158,11 +158,16 @@ static void ls1021_pcie_host_init(struct pcie_port *pp)
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static int ls_pcie_link_up(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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- u32 state;
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+ u32 state, offset;
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+
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+ if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL))
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+ offset = 0x407fc;
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+ else
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+ offset = PCIE_LUT_DBG;
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- state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
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- pcie->drvdata->ltssm_shift) &
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- LTSSM_STATE_MASK;
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+ state = (ioread32(pcie->lut + offset) >>
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+ pcie->drvdata->ltssm_shift) &
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+ LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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--
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1.7.9.5
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