mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 14:37:57 +00:00
799d0dddf6
The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
36 lines
958 B
Diff
36 lines
958 B
Diff
From cb8a47d43caa2b07a62d81ee0b65c0d16560c276 Mon Sep 17 00:00:00 2001
|
|
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
|
Date: Fri, 3 Jun 2016 13:15:28 +0530
|
|
Subject: [PATCH 229/238] drivers: clk: qoriq: Add ls2088a key to chipinfo
|
|
table
|
|
|
|
---
|
|
drivers/clk/clk-qoriq.c | 11 +++++++++++
|
|
1 file changed, 11 insertions(+)
|
|
|
|
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
|
|
index 164ac41..6185d6a 100644
|
|
--- a/drivers/clk/clk-qoriq.c
|
|
+++ b/drivers/clk/clk-qoriq.c
|
|
@@ -559,6 +559,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
|
|
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
|
|
},
|
|
{
|
|
+ .compat = "fsl,ls2088a-clockgen",
|
|
+ .cmux_groups = {
|
|
+ &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
|
|
+ },
|
|
+ .cmux_to_group = {
|
|
+ 0, 0, 1, 1, -1
|
|
+ },
|
|
+ .pll_mask = 0x37,
|
|
+ .flags = CG_VER3 | CG_LITTLE_ENDIAN,
|
|
+ },
|
|
+ {
|
|
.compat = "fsl,p2041-clockgen",
|
|
.guts_compat = "fsl,qoriq-device-config-1.0",
|
|
.init_periph = p2041_init_periph,
|
|
--
|
|
1.7.9.5
|
|
|