mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
53 lines
2.0 KiB
Diff
53 lines
2.0 KiB
Diff
From 6e5099288c946037476abd1488e4c7ab6b818e2b Mon Sep 17 00:00:00 2001
|
|
From: Annaliese McDermond <nh6z@nh6z.net>
|
|
Date: Wed, 3 Apr 2019 21:01:55 -0700
|
|
Subject: [PATCH] ASoC: tlv320aic32x4: Add Playback PowerTune Controls
|
|
|
|
commit d3e6e374566e1154820a9a3dc82f7eef646fcf95 upstream.
|
|
|
|
PowerTune controls the power level of the chip. On playback this
|
|
indirectly controls things like the gain of the various output
|
|
amplifiers. This can allow for the decrease of output levels
|
|
from the codec. This adds controls for those power levels to
|
|
the driver.
|
|
|
|
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
|
|
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
---
|
|
sound/soc/codecs/tlv320aic32x4.c | 9 +++++++++
|
|
sound/soc/codecs/tlv320aic32x4.h | 2 ++
|
|
2 files changed, 11 insertions(+)
|
|
|
|
--- a/sound/soc/codecs/tlv320aic32x4.c
|
|
+++ b/sound/soc/codecs/tlv320aic32x4.c
|
|
@@ -248,9 +248,18 @@ static const char * const lo_cm_text[] =
|
|
|
|
static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
|
|
|
|
+static const char * const ptm_text[] = {
|
|
+ "P3", "P2", "P1",
|
|
+};
|
|
+
|
|
+static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
|
|
+static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
|
|
+
|
|
static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
|
|
SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
|
|
AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
|
|
+ SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
|
|
+ SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
|
|
SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
|
|
AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
|
|
tlv_driver_gain),
|
|
--- a/sound/soc/codecs/tlv320aic32x4.h
|
|
+++ b/sound/soc/codecs/tlv320aic32x4.h
|
|
@@ -78,6 +78,8 @@ int aic32x4_register_clocks(struct devic
|
|
|
|
#define AIC32X4_PWRCFG AIC32X4_REG(1, 1)
|
|
#define AIC32X4_LDOCTL AIC32X4_REG(1, 2)
|
|
+#define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3)
|
|
+#define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4)
|
|
#define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9)
|
|
#define AIC32X4_CMMODE AIC32X4_REG(1, 10)
|
|
#define AIC32X4_HPLROUTE AIC32X4_REG(1, 12)
|